UM0434 datasheet(170/390 Pages) STMICROELECTRONICS

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UM0434

Interrupts and exceptions

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Checkstop state

The following exception conditions can cause a checkstop if MSR[ME]=0:

●

A machine check occurs.

●

First instruction in an interrupt handler cannot be executed due to a translation miss

(ITLB), a page marked no execute (ISI), or a bus error termination.

●

Bus error termination for a buffered store .

●

Precise external termination error occurs and MSR[EE]=0.

Non-exception–related checkstop conditions are as follows:

●

TCR[WRC] - Watchdog reset control bits set to checkstop on second watchdog timer

overflow event

When a processor is in checkstop state, instruction processing is suspended and generally

cannot resume without the processor being reset. To indicate that a checkstop condition

exists, the

p_chkstop output is asserted whenever the CPU is in checkstop state.

When a debug request is presented to the e200z3 core while it is in checkstop state,

p_wakeup is asserted, and when m_clk is provided to the core, it temporarily exits

checkstop state and enters debug mode. The

p_chkstop output is negated while the core

remains in a debug session (

p_debug_b asserted). When the debug session is exited, the

core re-enters checkstop state. Note that the external system logic may be in an undefined

state following a checkstop condition, such as having an outstanding bus transaction or

other inconsistency; thus, no guarantee can be made in general about activities performed

in debug mode while a checkstop is outstanding. Debug logic can generate assertion of

p_resetout_b through DBCR0.

6.6.3

Data storage interrupt (IVOR2)

A data storage interrupt may occur if no higher priority exception exists and one of the

following exists:

●

Read or write access control exception condition

●

Byte-ordering exception condition

●

External termination error (precise) and MSR[EE]=1

Access control is defined as in Book E. A byte-ordering exception condition occurs for any

misaligned access across a page boundary to pages with mismatched E bits. Precise

external termination errors occur when a load or guarded store is terminated by assertion of

p_d_tea_b=ERROR termination response.

Table 127 lists register settings when a DSI is taken.

Table 127.

Data storage interrupt register settings

Setting description

SRR0

Set to the effective address of the excepting load/store instruction

SRR1

Set to the contents of the MSR at the time of the interrupt

MSR

UCLE

SPE

—

FE0

—

FE1

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