UM0434 datasheet(173/390 Pages) STMICROELECTRONICS

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Interrupts and exceptions

UM0434

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place of the value in IVOR4 when an external input interrupt request is not autovectored

(

p_avec_b negated when p_extint_b asserted).

6.6.6

Alignment interrupt (IVOR5)

The e200z3 implements the alignment interrupt as defined by Book E. An alignment

exception is generated when any of the following occurs:

●

The operand of lmw or stmw is not word-aligned.

●

The operand of lwarx or stwcx. is not word-aligned.

●

Execution of dcbz is attempted

●

Execution is attempted of an SPE APU load or store instruction that is not properly

aligned.

Table 131 lists register settings when an alignment interrupt is taken.

6.6.7

Program interrupt (IVOR6)

The e200z3 implements the program interrupt as defined by Book E. A program interrupt

occurs when no higher priority exception exists and one or more of the following exception

conditions defined in Book E occur:

●

Illegal instruction exception

●

Privileged instruction exception

●

Trap exception

●

Unimplemented operation exception

The e200z3 invokes an illegal instruction program exception on attempted execution of the

following instructions:

●

Instruction from the illegal instruction class

●

mtspr and mfspr instructions that specify an undefined SPR

●

mtdcr and mfdcr instructions that specify an undefined DCR

Table 131.

Alignment interrupt register settings

Setting description

SRR0

Set to the effective address of the excepting load/store instruction.

SRR1

Set to the contents of the MSR at the time of the interrupt

MSR

UCLE

SPE

—

FE0

—

FE1

ESR

[ST], [VLEMI

]. All other bits cleared.

MCSR

Unchanged

DEAR

Set to the effective address of a byte of the load or store whose access caused the

violation.

Vector

IVPR[32–47] || IVOR5[48–59] || 0b0000

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