UM0434 datasheet(169/390 Pages) STMICROELECTRONICS

169 / 390 page

Interrupts and exceptions

UM0434

170/391

processor generates an internal checkstop condition and enters checkstop state. When a

processor is in checkstop state, instruction processing is suspended and generally cannot

continue without restarting the processor. Note that other conditions may lead to the

checkstop condition; the disabled machine check exception is only one of these.

The e200z3 implements MCSR to record the sources of machine checks. See

Chapter 6.4.1: Machine check syndrome register (MCSR) on page 166,” for more

information.

MSR[DE] is not automatically cleared by a machine check exception but can be configured

to be cleared or left unchanged through HID0[MCCLRDE]. See

Chapter 4.13.1: Hardware

implementation dependent register 0 (HID0) on page 84.”

Machine check interrupt enabled (MSR[ME]=1)

Machine check interrupts are enabled when MSR[ME]=1. When a machine check interrupt

is taken, registers are updated as shown in

Table 126.

The machine check input,

p_mcp_b, can be masked by HID0[EMCP].

Most machine check exceptions are unrecoverable in the sense that execution cannot

resume in the context that existed before the interrupt. However, system software can use

the machine check interrupt handler to try to identify and recover from the machine check

condition. In particular, the MCSR is provided to identify the sources of a machine check

and may be used to identify recoverable events.

The interrupt handler should set MSR[ME] as early as possible to avoid entering checkstop

state if another machine check condition occurs.

Table 126.

Machine check interrupt register settings

Setting description

CSRR0

On a best-effort basis, the e200z3 sets this to the address of some instruction that was

executing or about to be executing when the machine check condition occurred.

CSRR1

Set to the contents of the MSR at the time of the interrupt

MSR

UCLE

SPE

0(1)

FE1

Cleared when the debug APU is disabled. Clearing of DE is optionally supported by control in HID0 when

the debug APU is enabled.

ESR

Unchanged

MCSR

Updated to reflect the sources of a machine check

DEAR

Unchanged unless machine check is due to a data access causing a cache parity error to

be signaled; updated with data access effective address in that case

Vector

IVPR[32–47] || IVOR1[48–59] || 0b0000

UM0434 Datasheet(PDF) 169 Page - STMicroelectronics

UM0434 Datasheet(HTML) 169 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL