UM0434 datasheet(165/390 Pages) STMICROELECTRONICS

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Interrupts and exceptions

UM0434

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6.4.1

Machine check syndrome register (MCSR)

When the core complex takes a machine check interrupt, it updates MCSR, shown in

Table 119, to identify machine check conditions. The MCSR also indicates whether the

source of a machine check condition is recoverable. When an MCSR bit is set, the core

complex asserts

p_mcp_out for system information.

Table 120 describes MCSR fields.

Interrupt vector prefix register (IVPR)

The IVPR, shown in

Table 121, is used during interrupt processing for determining the

starting address for the software interrupt handler. The value contained in the vector offset

field of the IVOR selected for a particular interrupt type is concatenated with the value in the

IVPR to form an instruction address from which execution is to begin.

Data address space

0 The core directs all data storage accesses to address space 0 (TS=0 in the relevant TLB entry).

1 The core directs all data storage accesses to address space 1 (TS=1 in the relevant TLB entry).

60–61

—

Reserved, should be cleared.

62–63

—

Reserved, should be cleared.

Table 118.

MSR field descriptions

Bits

Name

Description

Table 119.

Machine check syndrome register (MCSR)

32 33

62 63

Field MCP — CP_PERR CPERR EXCP_ERR

—

BUS_IRERRBUS_DRERR BUS_WRERR —

Reset

All zeros

R/W

Table 120.

MCSR field Descriptions

Bits

Name

Description

Recoverable

MCP

Machine check input pin

Maybe

—

Reserved, should be cleared.

—

CP_PERR

Cache push parity error(1)

Unlikely

CPERR

Cache parity error1

Precise

EXCP_ERR

ISI, ITLB, or bus error on first instruction fetch for an interrupt handler

Precise

37–58

—

Reserved, should be cleared.

—

BUS_IRERR

Read bus error on instruction fetch

Unlikely

BUS_DRERR

Read bus error on data load

Unlikely

BUS_WRERR

Write bus error on buffered store or cache line push

Unlikely

62–63

—

Reserved, should be cleared.

—

This bit is implemented but must never be set by hardware.

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