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UM0434

Interrupts and exceptions

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6.3

Exception syndrome register (ESR)

ESR, shown in

Table 115, provides a syndrome to distinguish exceptions that can generate

the same interrupt type. The e200z3 adds some implementation-specific bits to this register.

The ESR fields are described in

Table 116.

Debug

Trap, instruction address compare, data address compare, instruction

complete, branch taken, return from interrupt, interrupt taken, debug

counter, external debug event, unconditional debug event

Chapter 6.6.16

Reserved

6–31 —

—

SPE unavailable

See

Chapter 6.6.18: SPE APU unavailable interrupt (IVOR32).”

Chapter 6.6.18

SPE data

See

Chapter 6.6.19: SPE Floating-Point data interrupt (IVOR33).”

Chapter 6.6.19

SPE round

See

Chapter 6.6.20: SPE Floating-Point round interrupt (IVOR34).”

Chapter 6.6.20

Vector to [p_rstbase[0:19]] || 0xFFC.

Autovectored external & critical input interrupts, use this IVOR. Vectored interrupts supply an interrupt vector offset directly.

Table 114.

Exceptions and conditions (continued)

Interrupt type

IVOR

Cause

Section/page

Table 115.

Exception syndrome register (ESR)

35 36

38 39 40 41 42

43 44

46 47 48

61 62

Field

—

PIL PPR PTR FP ST — DLK ILK AP PUO BO PIE

—

SPE — VLEMI

—

MIF XTE

Reset

All zeros

R/W

SPR

SPR 62

Table 116.

ESR field descriptions

Bit(s)

Name

Description

Associated interrupt type

32–35

—

Reserved, should be cleared.

—

PIL

Illegal instruction exception

Program

PPR

Privileged instruction exception

Program

PTR

Trap exception

Program

Floating-point operation

Alignment, data storage, data TLB, program

Store operation

Alignment, data storage, data TLB

—

Reserved, should be cleared.

—

DLK

Data cache locking(1)

Data storage

ILK

Instruction cache locking

Data storage`

Auxiliary processor operation. (unused in the

e200z3)

Alignment, data storage, data TLB, program

PUO

Unimplemented operation exception

Program

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