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Interrupts and exceptions

UM0434

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Interrupts and exceptions

This chapter provides a general description of the PowerPC Book E interrupt and exception

model and gives details of the additions and changes to that model that are implemented in

the e200z3 core. This chapter identifies features defined by Book E, the Freescale Book E

implementation standards (EIS), and the e200z3 implementation.

6.1

Overview

Book E defines the mechanisms by which the e200z3 core implements interrupts and

exceptions. Note the following definitions:

Interrupt

Action in which the processor saves its old context and begins

execution at a predetermined interrupt handler address

Exceptions

Events that, if enabled, cause the processor to take an interrupt

The PowerPC exception mechanism allows the processor to change to supervisor state for

the following reasons:

●

As a result of unusual conditions (exceptions) arising in the execution of instructions

●

As a response to the assertion of external signals, bus errors, or various internal

conditions

When an interrupt occurs, information about the processor state held in the MSR and the

address at which execution should resume after the interrupt is handled are saved to a pair

of save/restore registers (SRR0/SRR1 for non-critical interrupts, CSRR0/CSRR1 for critical

interrupts, or DSRR0/DSRR1 for debug interrupts when the debug APU is enabled), and the

processor begins executing at an address (interrupt vector) determined by the interrupt

vector prefix register (IVPR) and an interrupt-specific interrupt vector offset register

(IVOR

n). Processing of instructions within the interrupt handler begins in supervisor mode.

Multiple exception conditions can map to a single interrupt vector and may be distinguished

by examining registers associated with the interrupt. The exception syndrome register

(ESR) is updated with information specific to the exception type when an interrupt occurs.

To prevent loss of state information, interrupt handlers must save the information stored in

the save/restore registers soon after the interrupt is taken. Hardware supports nesting of

critical interrupts within non-critical interrupts, and debug interrupts within both critical and

non-critical interrupts. The interrupt handler must save necessary state information if

interrupts of a given class are re-enabled within the handler.

The following terms are used to describe the stages of exception processing:

Recognition

Exception recognition occurs when the condition that can

cause an exception is identified by the processor.

Recognition is also referred to as an ‘exception event.’

Taken

An interrupt is said to be taken when control of instruction

execution is passed to the interrupt handler; that is, the context

is saved, the instruction at the appropriate vector offset is fetched,

and the interrupt handler routine begins.

Handling

Interrupt handling is performed by the software linked to the appropriate

vector offset. Interrupt handling is begun in supervisor mode.

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