UM0434 datasheet(160/390 Pages) STMICROELECTRONICS

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UM0434

Interrupts and exceptions

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Returning from an interrupt is performed by executing the appropriate return from interrupt

instruction (rfi, rfci, or rfdi), which restores state information from their respective

save/restore registers and returns instruction fetching to the interrupted flow.

6.2

e200z3 interrupts

The Book E architecture specifies that interrupts can be precise or imprecise, synchronous

or asynchronous, and critical or non-critical. These characteristics are described as follows:

●

Asynchronous exceptions are caused by events external to the processor’s instruction

execution.

●

Synchronous exceptions are directly caused by instructions or by an event somehow

synchronous to the program flow, such as a context switch.

●

A precise interrupt architecturally guarantees that no instruction beyond the instruction

causing the exception has (visibly) executed. An imprecise interrupt does not have this

guarantee.

●

Book E defines critical and non-critical interrupt types, and the e200z3 defines an

implementation-specific debug APU that includes the debug interrupt type. Each

interrupt type provides separate resources (save/restore registers and return from

interrupt instructions) that allow interrupts of one type to not interfere with the state

handling of an interrupt of another type.

Table 113 describes how these apply to the interrupts implemented by the e200z3 core.

The classifications in

Table 113 are discussed in greater detail in Chapter 6.6: Interrupt

definitions on page 168.” Interrupts implemented in the e200z3 and the exception conditions

that cause them, are listed in

Table 114. Note that although this table lists system reset,

Book E does not define system reset as an interrupt and assigns no interrupt vector to it.

Table 113.

Interrupt classifications

Interrupt types

Synchronous /

asynchronous

Precise /

imprecise

Critical / non-critical

/ debug

System reset

Asynchronous,

non-maskable

Imprecise

—

Machine check

—

Critical

Critical input

Watchdog timer

Asynchronous,

maskable

Imprecise

Critical

External input

Fixed-interval timer

Decrementer

Asynchronous,

maskable

Imprecise

Non-critical

Instruction based debug

Synchronous

Precise

Critical/debug

Debug (UDE)

Debug imprecise

Asynchronous

Imprecise

Critical/debug

Data storage

/ alignment / TLB

Instruction storage / TLB

Synchronous

Precise

Non-critical

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