UM0434 datasheet(171/390 Pages) STMICROELECTRONICS

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Interrupts and exceptions

UM0434

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6.6.4

Instruction storage interrupt (IVOR3)

An instruction storage interrupt (ISI) occurs when no higher priority exception exists and an

execute access control exception occurs. This interrupt is implemented as defined by

Book E, except for the following:

●

The byte-ordering condition does not occur in the e200z3

●

The addition of precise external termination errors that occur when an instruction fetch

is terminated by assertion of a

p_i_tea_b=ERROR termination response and

MSR[EE]=1

●

Misaligned instruction fetch exceptions

●

The extension of the byte ordering exception cases.

Exception extensions implemented in e200z3 for VLE involve extending the definition of the

instruction storage interrupt to include the following:

●

Byte-ordering exceptions for instruction accesses

●

Misaligned instruction fetch exceptions

●

Corresponding updates to the ESR as shown in

Table 128 and Table 129

Table 129 lists register settings when an ISI is taken.

ESR

Access:

Byte ordering:

External termination error

(precise):

[ST], [VLEMI ]. All other bits cleared.

[ST], [VLEMI ], BO. All other bits cleared.

[ST], [VLEMI ], XTE. All other bits cleared.

MCSR

Unchanged

DEAR

For access and byte-ordering exceptions, set to the effective address of a byte within the page whose

access caused the violation.

Vector

IVPR[32–47] || IVOR2[48–59] || 0b0000

Table 127.

Data storage interrupt register settings (continued)

Setting description

Table 128.

ISI exceptions and conditions

Interrupt

type

IVOR

Causing conditions

Instruction

storage

IVOR

– Access control.

– Precise external termination error (

p_tea_b assertion and precise recognition) and

MSR[EE]=1.

– Byte ordering due to misaligned instruction across page boundary to pages with

mismatched VLE bits, or access to page with VLE set, and E indicating little-endian.

– Misaligned Instruction fetch due to a change of flow to an odd halfword instruction

boundary on a Book E (non-VLE) instruction page, due to value in LR, CTR, or xSRR0

Table 129.

Instruction storage interrupt register settings

Setting description

SRR0

Set to the effective address of the excepting instruction.

SRR1

Set to the contents of the MSR at the time of the interrupt

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