UM0434 datasheet(175/390 Pages) STMICROELECTRONICS

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Interrupts and exceptions

UM0434

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6.6.9

System call interrupt (IVOR8)

A system call interrupt occurs when a system call (sc, se_sc) is executed and no higher

priority exception exists. Exception extensions implemented in e200z3 for VLE include

modification of the system call interrupt definition to include updating the ESR.

Table 134 lists register settings when a system call interrupt is taken.

6.6.10

Auxiliary processor unavailable interrupt (IVOR9)

An APU exception is defined by Book E to occur when an attempt is made to execute an

APU instruction which is implemented but configured as unavailable, and no higher priority

exception condition exists.

The e200z3 does not use this interrupt.

MSR

UCLE

SPE

—

FE0

—

FE1

ESR

Unchanged

MCSR

Unchanged

DEAR

Unchanged

Vector

IVPR[32–47] || IVOR7[48–59] || 0b0000

Table 133.

Floating-Point unavailable interrupt register Settings

Setting Description

Table 134.

System call interrupt register settings

Setting Description

SRR0

Set to the effective address of the instruction

following the sc instruction.

SRR1

Set to the contents of the MSR at the time of the interrupt

MSR

UCLE

SPE

—

FE0

—

FE1

ESR

[VLEMI]. All other bits cleared.

MCSR

Unchanged

DEAR

Unchanged

Vector

IVPR[32–47] || IVOR8[48–59] || 0b0000

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