UM0434 datasheet(178/390 Pages) STMICROELECTRONICS

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UM0434

Interrupts and exceptions

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6.6.14

Data TLB error interrupt (IVOR13)

A data TLB error interrupt occurs when no higher priority exception exists and a data TLB

error exception occurs due to a data TLB miss.

Table 138 lists register settings for DTLB

interrupts.

6.6.15

Instruction TLB error interrupt (IVOR14)

An instruction TLB error interrupt occurs when no higher priority exception exists and an

instruction TLB error exception exists due to an instruction translation lookup miss in the

TLB.

Table 139 lists register settings when an ITLB interrupt is taken.

Table 138.

Data TLB error interrupt register settings

Setting description

SRR0

Set to the effective address of the excepting load/store instruction.

SRR1

Set to the contents of the MSR at the time of the interrupt

MSR

UCLE

SPE

—

FE0

—

FE1

ESR

[ST], [SPE], [VLEMI]. All other bits cleared.

MCSR

Unchanged

DEAR

Set to the effective address of a byte of the load or store whose access caused the

violation.

Vector

IVPR[32–47] || IVOR13[48–59] || 0b0000

Table 139.

Instruction TLB error interrupt register settings

Setting description

SRR0

Set to the effective address of the excepting instruction.

SRR1

Set to the contents of the MSR at the time of the interrupt

MSR

UCLE

SPE

—

FE0

—

FE1

ESR

[MIF] All other bits cleared.

MCSR

Unchanged

DEAR

Unchanged

Vector

IVPR[32–47] || IVOR14[48–59] || 0b0000

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