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UM0434 Datasheet(PDF) 182 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 182 Page - STMicroelectronics |
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182 / 390 page ![]() UM0434 Interrupts and exceptions 183/391 When a reset request occurs, the processor branches to the system reset exception vector (value on p_rstbase[0:19] concatenated with 0xFFC) without attempting to reach a recoverable state. If reset occurs during normal operation, all operations stop and machine state is lost. The internal state of the e200z6e200z3 after a reset is defined in Chapter 4.18.4: Reset settings.” For reset initiated by watchdog timer or debug reset control, the e200z6 implements TSR[WRS] or DBSR[MRR] to help software determine the cause. Watchdog timer and debug reset control provide the capability to assert p_resetout_b. External logic may factor this signal into p_reset_b to cause an e200z6e200z3 reset. Table 142 shows the TSR bits associated with reset status. Table 143 shows the DBSR bits associated with reset status. Table 144 lists register settings when a system reset is taken. 6.6.18 SPE APU unavailable interrupt (IVOR32) The SPE APU unavailable exception is taken if MSR[SPE] is cleared and execution of an SPE APU instruction other than an embedded scalar floating-point or brinc instruction is attempted. When the SPE APU unavailable exception occurs, the processor suppresses Table 142. TSR watchdog timer reset status Bits Name Description 34–35 WRS 00 No action performed by watchdog timer 01 Watchdog timer second timeout caused checkstop. 10 Watchdog timer second timeout caused p_resetout_b to be asserted. 11 Reserved Table 143. DBSR most recent reset Bits Name Function 34–35 MRR 00 No reset occurred since these bits were last cleared by software. 01 A reset occurred since these bits were last cleared by software. 1 x Reserved Table 144. System reset register Settings Register Setting description CSRR0 Undefined CSRR1 Undefined MSR UCLE 0 WE 0 CE 0 EE 0 PR 0 FP 0 ME 0 DE 0 FE1 0 IS 0 DS 0 ESR Cleared DEAR Undefined Vector [ p_rstbase[0:19]] || 0xFFC |
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