Electronic Components Datasheet Search
  English  ▼

X  

UM0434 Datasheet(PDF) 182 Page - STMicroelectronics

Part # UM0434
Description  The primary objective of this user?셲 manual is to describe
PDF  390 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UM0434 Datasheet(HTML) 182 Page - STMicroelectronics

Back Button UM0434 Datasheet HTML 178Page - STMicroelectronics UM0434 Datasheet HTML 179Page - STMicroelectronics UM0434 Datasheet HTML 180Page - STMicroelectronics UM0434 Datasheet HTML 181Page - STMicroelectronics UM0434 Datasheet HTML 182Page - STMicroelectronics UM0434 Datasheet HTML 183Page - STMicroelectronics UM0434 Datasheet HTML 184Page - STMicroelectronics UM0434 Datasheet HTML 185Page - STMicroelectronics UM0434 Datasheet HTML 186Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 182 / 390 page
background image
UM0434
Interrupts and exceptions
183/391
When a reset request occurs, the processor branches to the system reset exception vector
(value on
p_rstbase[0:19] concatenated with 0xFFC) without attempting to reach a
recoverable state. If reset occurs during normal operation, all operations stop and machine
state is lost. The internal state of the e200z6e200z3 after a reset is defined in
Chapter 4.18.4: Reset settings.”
For reset initiated by watchdog timer or debug reset control, the e200z6 implements
TSR[WRS] or DBSR[MRR] to help software determine the cause. Watchdog timer and
debug reset control provide the capability to assert
p_resetout_b. External logic may factor
this signal into
p_reset_b to cause an e200z6e200z3 reset.
Table 142 shows the TSR bits associated with reset status.
Table 143 shows the DBSR bits associated with reset status.
Table 144 lists register settings when a system reset is taken.
6.6.18
SPE APU unavailable interrupt (IVOR32)
The SPE APU unavailable exception is taken if MSR[SPE] is cleared and execution of an
SPE APU instruction other than an embedded scalar floating-point or brinc instruction is
attempted. When the SPE APU unavailable exception occurs, the processor suppresses
Table 142.
TSR watchdog timer reset status
Bits
Name
Description
34–35
WRS
00 No action performed by watchdog timer
01 Watchdog timer second timeout caused checkstop.
10 Watchdog timer second timeout caused
p_resetout_b to be asserted.
11 Reserved
Table 143.
DBSR most recent reset
Bits
Name
Function
34–35
MRR
00 No reset occurred since these bits were last cleared by software.
01 A reset occurred since these bits were last cleared by software.
1
x Reserved
Table 144.
System reset register Settings
Register
Setting description
CSRR0
Undefined
CSRR1
Undefined
MSR
UCLE
0
WE
0
CE
0
EE
0
PR
0
FP
0
ME
0
DE
0
FE1
0
IS
0
DS
0
ESR
Cleared
DEAR
Undefined
Vector
[
p_rstbase[0:19]] || 0xFFC



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com