UM0434 datasheet(183/390 Pages) STMICROELECTRONICS

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Interrupts and exceptions

UM0434

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execution of the instruction causing the exception.

Table 145 lists register settings when an

SPE unavailable interrupt is taken.

6.6.19

SPE Floating-Point data interrupt (IVOR33)

The SPE floating-point data interrupt is taken if no higher priority exception exists and an

SPE floating-point data exception is generated. When a floating-point data exception

occurs, the processor suppresses execution of the instruction causing the exception.

Table 146 lists register settings when an SPE floating-point data interrupt is taken.

Table 145.

SPE unavailable interrupt register settings

Setting description

SRR0

Set to the effective address of the excepting SPE instruction

SRR1

Set to the contents of the MSR at the time of the interrupt

MSR

UCLE

SPE

—

FE0

—

FE1

ESR

SPE, [VLEMI]. All other bits cleared.

MCSR

Unchanged

DEAR

Unchanged

Vector

IVPR[32–47] || IVOR32[48–59] || 0b0000

Table 146.

SPE Floating-Point data interrupt register settings

Setting description

SRR0

Set to the effective address of the excepting SPE instruction.

SRR1

Set to the contents of the MSR at the time of the interrupt

MSR

UCLE

SPE

—

FE0

—

FE1

ESR

SPE, [VLEMI]. All other bits cleared.

MCSR

Unchanged

DEAR

Unchanged

Vector

IVPR[32–47] || IVOR33[48–59] || 0b0000

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