| Electronic Components Datasheet Search |
|
UM0434 Datasheet(PDF) 212 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
UM0434 Datasheet(HTML) 212 Page - STMicroelectronics |
|
212 / 390 page ![]() UM0434 Instruction pipeline and execution timing 213/391 Back-to-back load/store instructions are executed in a pipelined fashion, provided that their EA calculations are not dependent on their previous load instructions. Figure 18 shows the basic pipeline flow for two back-to-back load instructions. In this case, the second load does not depend on its previous load data for its EA calculation. Notice that the memory access of the first load instruction overlaps in time with the EA calculation of the second load instruction. Figure 18. Back-to-Back load instructions When a load is followed by a load or a store instruction that depends on the first load data for EA calculation, a pipeline stall is incurred. Figure 19 shows the instruction flow for a load instruction followed by a dependent store instruction through EA calculation. The second store instruction in this case is dependent on the first load instruction for its EA calculation. Figure 19. A load followed by a dependent store instruction A store instruction that depends on its previous load for its stored data, does not stall the pipeline. 8.3.5 Change-of-Flow instruction pipeline operation A branch instruction takes either one or 2 cycles to execute. Simple change of flow instructions require 2 cycles to refill the pipeline with the target instruction for taken branches and branch and link instructions with no prediction. For branch-type instructions, in some situations, this 2-cycle timing may be reduced by performing the target fetch speculatively while the branch instruction is still being fetched into the instruction buffer. The branch target address is obtained from the BTB. The resulting branch timing reduces to a single clock when the target fetch is initiated early enough and the branch is taken. Figure 20 shows basic pipeline flow for branch instructions. DEC / EA MEM First Load Instruction Time Slot WB Second Load Instruction DEC / EA MEM WB IFETCH IFETCH DECODE EXECUTE First Load Instruction Time Slot WB Second Store Instruction DECODE EA Calc MEM IFETCH IFETCH WB Feedforward |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |