UM0434 datasheet(216/390 Pages) STMICROELECTRONICS

216 / 390 page

UM0434

Instruction pipeline and execution timing

217/391

Figure 27.

DCR, MMU mtspr, mfspr, and MMU management instruction execution

8.4

Stalls caused by accessing SPRs

An mfspr instruction preceded by an mtspr instruction cannot be issued until the mtspr

completes.

8.5

Instruction serialization

The core requires three types of serialization:

●

Completion serialization. A completion-serialized instruction is held for execution until

all prior instructions have completed. The instruction executes when it is next to

complete in program order. Results from these instructions are not available for or

forwarded to subsequent instructions until the instruction completes. The following

instructions are completion-serialized:

–

Instructions that access or modify system control or status registers—mcrxr,

mtmsr, wrtee, wrteei, mtspr, mfspr (except to CTR/LR)

–

Instructions that manage TLBs

–

Instructions defined by the architecture as context or execution synchronizing:

isync, msync, rfi, rfci, rfdi, and sc

●

Dispatch (decode/issue) serialization. Some instructions are dispatch-serialized by the

core. An instruction that is dispatch-serialized prevents the next instruction from

decoding until all instructions up to and including the dispatch-serialized instruction

Time Slot

DEC

EXE

IFETCH

...

Single-Cycle Instruction

DEC

Stall

IFETCH

Stall

EXE

Next Instruction

p_[i,d]_treq_b

p_[i,d]_tbusy[0]_b

p_[i,d]_ta_b

p_rd_spr,

p_wr_spr

p_[i,d]_cmbusy

mtspr, mfspr

DEC

Stall

IFETCH

Stall

EXE

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