UM0434 datasheet(217/390 Pages) STMICROELECTRONICS

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Instruction pipeline and execution timing

UM0434

218/391

completes. The isync, mbar, msync, rfi, rfci, rfdi, and sc instructions are dispatch-

serialized.

●

Refetch serialization. Refetch-serialized instructions inhibit dispatching of subsequent

instructions and force a pipeline refill to refetch subsequent instructions after

completion. These include the following:

–

The context synchronizing instruction isync

–The rfi, rfci, rfdi, and sc instructions.

8.6

Interrupt recognition and exception processing

Figure 28 shows timing for interrupt recognition and exception processing overhead. This

example shows best-case response timing when an interrupt is received and processed

during execution of a sequence of single-cycle instructions.

Figure 28.

Interrupt recognition and handler instruction execution

Time Slot

IFETCH

EXE

DEC

Single cycle

Instructions

DEC/

IFETCH

p_extint_b

final sample point

p_iack

IFETCH

EXE

DEC

1st Instruction of handler

123456789

ec_excp_detected*

update_esr*

update_msr*

* - internal operations

oldpc_->srr0*

oldmsr_->srr1*

Abort

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