UM0434 datasheet(219/390 Pages) STMICROELECTRONICS

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Instruction pipeline and execution timing

UM0434

220/391

Figure 30 below, shows timing for interrupt recognition and exception processing overhead.

This example shows best-case response timing when an interrupt is received and

processed during execution of a multicycle interruptible instruction.

Figure 30.

Interrupt recog. & handler instruction exe-multi-cycle instruction abort

8.7

Instruction timings

Table shows instruction timing for various instruction classes. Pipelined instructions are

shown with cycles of total latency and throughput. Divide instructions are not pipelined and

block other instructions from executing during divide execution.

Load/store multiple instruction cycles are represented as a fixed number of cycles plus a

variable number of cycles where ‘n’ is the number of words accessed by the instruction.

Additionally, cycle times marked with an ampersand (&) require additional cycles due to

serialization.

Time Slot

Next Instruction

IFETCH

EXE

Abort

DEC

Multi-Cycle

Interruptible

IFETCH

Abort

DEC

1234567

p_extint_b

Final Sample Point

p_iack

IFETCH

EXE

DEC

First Instruction of handler

ec_excp_detected*

oldpc_->srr0*

oldmsr_->srr1*

update_esr*

update_msr*

* Internal Operations

Instruction

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