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UM0434 Datasheet(PDF) 227 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 227 Page - STMicroelectronics |
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227 / 390 page  Instruction pipeline and execution timing UM0434 228/391 SPE load and store instruction timing Instruction timing for SPE load and store instructions is shown in Table 160. The table is sorted by opcode. Actual timing depends on alignment; the table indicates timing for aligned operands. evsrws 11 evsrwu 11 evsubfw 11 evsubifw 11 evxor 11 Table 160. SPE load and store instruction timing Instruction Latency Throughput Comments evldd 11 evlddx 11 evldh 11 evldhx 11 evldw 11 evldwx 11 evlhhesplat 11 evlhhesplatx 11 evlhhossplat 11 evlhhossplatx 11 evlhhousplat 11 evlhhousplatx 11 evlwhe 11 evlwhex 11 evlwhos 11 evlwhosx 11 evlwhou 11 evlwhoux 11 evlwhsplat 11 evlwhsplatx 11 evlwwsplat 11 evlwwsplatx 11 evstdd 11 Table 159. Timing for integer simple instructions (continued) Instruction Latency Throughput Comments |
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