UPD784021 datasheet(29/90 Pages) NEC

29 / 90 page

mPD784020, 784021

Table 8-1 Port Functions

8.2

CLOCK GENERATOR

A circuit for generating the clock signal required for operation is provided. The clock generator includes a frequency

divider; low current consumption can be achieved by operating at a lower internal frequency when high-speed

operation is not necessary.

Fig. 8-2 Block Diagram of Clock Generator

Remark fXX : Oscillator frequency or external clock input

fCLK: Internal operating frequency

Port name

Function

Pull-up specification by software

Port 0

P00-P07

• Bit-by-bit input/output setting supported

Specified as a batch for all pins placed in

• Operable as 4-bit real-time outputs

input mode.

(P00-P03, P04-P07)

• Capable of driving transistors

Port 1

P10-P17

• Bit-by-bit input/output setting supported

Specified as a batch for all pins placed in

• Capable of driving LEDs

input mode.

Port 2

P20-P27

• Input port

Specified for the 6 bits (P22-P27) as a batch.

Port 3

P30-P37

• Bit-by-bit input/output setting supported

Specified as a batch for all pins placed in

input mode.

Port 6

P60-P63

• Output-only port

P66, P67

• Bit-by-bit input/output setting supported

Port 7

P70-P77

• Bit-by-bit input/output setting supported

—

Specified as a batch for all pins placed in

input mode.

fXX/2

fXX

fCLK

CPU

Peripheral circuits

Oscillator

UART/IOE

INTP0 noise eliminator

Oscillation settling timer

1/2

UPD784021 Datasheet(PDF) 29 Page - NEC

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