UPD784021 datasheet(69/90 Pages) NEC

69 / 90 page

mPD784020, 784021

SERIAL OPERATION (IOE1, IOE2)

Remarks 1. The values listed in the above table are obtained when CL = 100 pF.

2. T: Serial clock frequency specified using software. The minimum value is 16/fXX.

SERIAL OPERATION (UART, UART2)

Unit

Min.

250

500

210

0.5T – 40

210

0.5T – 40

0.5TCYSK1 – 40

Max.

Conditions

Input

VDD = +5.0 V

±10 %

Output

Internal clock divided by 16

Input

VDD = +5.0 V

±10 %

Output

Internal clock divided by 16

Input

VDD = +5.0 V

±10 %

Output

Internal clock divided by 16

During data transfer

Symbol

tCYSK1

tWSKL1

tWSKH1

tSSSK1

tHSSK1

tDSOSK

tHSOSK

Parameter

Serial clock cycle time

(SCK1, SCK2)

Serial clock low-level width

(SCK1, SCK2)

Serial clock high-level width

(SCK1, SCK2)

SI1, SI2 setup time

(referred to SCK1, SCK2

•)

SI1, SI2 hold time

(referred to SCK1, SCK2

•)

SO1, SO2 output delay time

(referred to SCK1, SCK2

Ø)

SO1, SO2 output hold time

(referred to SCK1, SCK2

•)

Parameter

ASCK clock input cycle time

ASCK clock low-level width

ASCK clock high-level width

Symbol

tCYASK

tWASKL

tWASKH

Unit

Min.

125

250

52.5

Max.

Conditions

VDD = +5.0 V

±10 %

VDD = +5.0 V

±10 %

VDD = +5.0 V

±10 %

UPD784021 Datasheet(PDF) 69 Page - NEC

UPD784021 Datasheet(HTML) 69 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

Datasheet Download

Link URL