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UPD784021 Datasheet(PDF) 67 Page - NEC

Part # UPD784021
Description  16/8-BIT SINGLE-CHIP MICROCOMPUTER
PDF  90 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD784021 Datasheet(HTML) 67 Page - NEC

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mPD784020, 784021
(3) External wait timing
Remark T:
TCYK (system clock cycle time)
a:
1 when address wait is applied, 0 in other cases
n:
number of wait cycles (n
• 0)
(4) Refresh timing
Remark T: TCYK (system clock cycle time)
Parameter
Address
Æ WAITØ input time
ASTB
Ø Æ WAITØ input time
ASTB
Ø Æ WAIT hold time
ASTB
Ø Æ WAIT• delay time
RD
Ø Æ WAITØ input time
RD
Ø Æ WAITØ hold time
RD
Ø Æ WAIT• delay time
WAIT
• Æ data input time
WAIT
• Æ WR• delay time
WAIT
• Æ RD• delay time
WR
Ø Æ WAITØ input time
WR
Ø Æ WAIT hold time
WR
Ø Æ WAIT• delay time
Symbol
tDAWT
tDSTWT
tHSTWTH
tDSTWTH
tDRWTL
tHRWT
tDRWTH
tDWTID
tDWTW
tDWTR
tDWWTL
tHWWT
tDWWTH
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min.
(0.5 + n) T + 5
(0.5 + n) T + 10
nT + 5
nT + 10
0.5T
0.5T
nT + 5
nT + 10
Max.
(2 + a) T – 40
(2 + a) T – 60
1.5T – 40
1.5T – 60
(1.5 + n) T – 40
(1.5 + n) T – 60
T – 50
T – 70
(1 + n) T – 40
(1 + n) T – 60
0.5T – 5
0.5T – 10
T – 50
T – 75
(1 + n) T – 40
(1 + n) T – 60
Conditions
VDD = +5.0 V
±10 %
VDD = +5.0 V
±10 %
VDD = +5.0 V
±10 %
VDD = +5.0 V
±10 %
VDD = +5.0 V
±10 %
VDD = +5.0 V
±10 %
VDD = +5.0 V
±10 %
VDD = +5.0 V
±10 %
VDD = +5.0 V
±10 %
VDD = +5.0 V
±10 %
VDD = +5.0 V
±10 %
Parameter
Random read/write cycle time
REFRQ low-level pulse width
ASTB
Ø Æ REFRQ delay time
RD
• Æ REFRQ delay time
WR
• Æ REFRQ delay time
REFRQ
• Æ ASTB delay time
REFRQ high-level pulse width
Symbol
tRC
tWRFQL
tDSTRFQ
tDRRFQ
tDWRFQ
tDRFQST
tWRFQH
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min.
3T
1.5T – 25
1.5T – 30
0.5T – 9
1.5T – 9
1.5T – 9
0.5T – 9
1.5T – 25
1.5T – 30
Max.
Conditions
VDD = +5.0 V
±10 %
VDD = +5.0 V
±10 %



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