UPD784021 datasheet(70/90 Pages) NEC

70 / 90 page

mPD784020, 784021

OTHER OPERATIONS

Remark tCYSMP: sampling clock specified using software

tCYCPU: CPU operating clock specified using CPU software

A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = 3.4 to 5.5 V, +3.4 V

£ AVREF1 £ AVDD,

VSS = AVSS = 0 V)

Note

Quantization error is excluded. The error is represented in percent with respect to a full-scale value.

Remark tCYK: system clock cycle time

Parameter

NMI low-level width

NMI high-level width

INTP0 low-level width

INTP0 high-level width

INTP1-INTP3 and CI low-

level width

INTP1-INTP3 and CI high-

level width

INTP4 and INTP5 low-level

width

INTP4 and INTP5 high-level

width

RESET low-level width

RESET high-level width

Symbol

tWNIL

tWNIH

tWIT0L

tWIT0H

tWIT1L

tWIT1H

tWIT2L

tWIT2H

tWRSL

tWRSH

Unit

Min.

3tCYSMP + 10

3tCYCPU + 10

Max.

Conditions

Parameter

Resolution

Total errorNote

Linearity calibrationNote

Quantization error

Conversion time

Sampling time

Analog input voltage

Analog input impedance

AVREF1 current

AVDD supply current

Symbol

tCONV

tSAMP

VIAN

RAN

AIREF1

AIDD1

AIDD2

Unit

bit

LSB

tCYK

Min.

120

180

–0.3

Typ.

1000

0.5

2.0

Max.

1.2

1.0

0.6

±1/2

AVREF1 + 0.3

1.5

5.0

Conditions

VDD = AVDD = +5.0 V

±10 %

+3.4 V

£ AVREF1 £ AVDD

+2.7 V

£ VDD = AVDD £ +3.3 V

+2.5 V

£ AVREF1 £ AVDD

tCYK

£ 500 ns, FR = 1

tCYK

£ 500 ns, FR = 0

tCYK

£ 500 ns, FR = 1

tCYK

£ 500 ns, FR = 0

fXX = 25 MHz

STOP mode, CS = 0

UPD784021 Datasheet(PDF) 70 Page - NEC

UPD784021 Datasheet(HTML) 70 Page - NEC

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