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TAS5548DCAR Datasheet(PDF) 16 Page - Texas Instruments |
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TAS5548DCAR Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 116 page ![]() 23 22 SCLK 32Clks LRCLK(NoteReversedPhase) LeftChannel 24-BitMode 1 19 18 20-BitMode 16-BitMode 15 14 MSB LSB 32Clks RightChannel 2-ChannelI S(PhilipsFormat)StereoInput 2 T0034-01 5 4 9 8 1 0 0 4 5 1 0 23 22 1 19 18 15 14 MSB LSB 5 4 9 8 1 0 0 4 5 1 0 SCLK TAS5548 SLES270A – NOVEMBER 2012 – REVISED APRIL 2015 www.ti.com 7.3 Feature Description 7.3.1 Serial Audio Interface Control and Timing 7.3.1.1 Input I2S Timing I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 64 fS is used to clock in the data. From the time the LRCLK signal changes state to the first bit of data on the data lines is a delay of one bit clock. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5548 masks unused trailing data bit positions. Figure 15. I2S 64-fS Format 16 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TAS5548 |
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