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TAS5548DCAR Datasheet(PDF) 75 Page - Texas Instruments |
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TAS5548DCAR Datasheet(HTML) 75 Page - Texas Instruments |
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75 / 116 page  TAS5548 www.ti.com SLES270A – NOVEMBER 2012 – REVISED APRIL 2015 7.6.2.26 DRC2 Control Register CH8 (0x97) – Write Register DRC Control selects which channels contribute to the expansion/compression evaluation using DRC2. The evaluation is global such that if one signal forces compression all DRC2 signals will be in compression. Table 44. Write Register Format D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION x x x x x x x x D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION x x x x x x x x D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION x x x x x x x x D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION x x x x x x 0 0 Channel 8: Not included in DRC evaluation x x x x x x 0 1 Channel 8: Pre-volume DRC x x x x x x 1 0 Channel 8: Post-volume DRC x x x x x x 1 1 Channel 8: Not included in DRC evaluation 7.6.2.27 DRC1 Data Registers (0x98–0x9C) DRC1 applies to channels 1, 2, 3, 4, 5, 6, and 7. Table 45. DRC1 Data Register Format I2C TOT AL SUB- REGISTER NAME DESCRIPTION OF CONTENTS DEFAULT STATE DATA DECIMAL BYTE ADDRES S S Channel 1, 2, 3, 4, 5, 6, and 7 u[31:28], E[27:24], E[23:16], E[15:8], E[7:0] 0000 883F mS DRC1 energy 0x98 8 Channel 1, 2, 3, 4, 5, 6, and 7 u[31:28], 1–E[27:24], 1–E[23:16], 1–E[15:8], 007F 77C0 DRC1 (1 – energy) 1–E[7:0] Channel 1, 2, 3, 4, 5, 6, and 7 T1[31:24], T1[23:16], T1[15:8], T1[7:0] 0B20 E2B2 dB DRC1 threshold lower 32 bits (T1) 0x99 8 Channel 1, 2, 3, 4, 5, 6, and 7 T2[31:24], T2[23:16], T2[15:8], T2[7:0] 06F9 DE58 dB DRC1 threshold lower 32 bits (T2) Channel 1, 2, 3, 4, 5, 6, and 7 u[31:28], k0[27:24], k0[23:16], k0[15:8], k0[7:0] 0040 0000 ratio DRC1 slope (k0) Channel 1, 2, 3, 4, 5, 6, and 7 u[31:28], k1[27:24], k1[23:16], k1[15:8], k1[7:0] 0FC0 0000 ratio 0x9A 12 DRC1 slope (k1) Channel 1, 2, 3, 4, 5, 6, and 7 u[31:28], k2[27:24], k2[23:16], k2[15:8], k2[7:0] 0F90 0000 ratio DRC1 slope (k2) Channel 1, 2, 3, 4, 5, 6, and 7 O1[31:24], O1[23:16], O1[15:8], O1[7:0] FF82 3098 dB DRC1 offset-1 lower 32 bits (O1) 0x9B 8 Channel 1, 2, 3, 4, 5, 6, and 7 O2[31:24], O2[23:16], O2[15:8], O2[7:0] 0195 B2C0 dB DRC1 offset-2 lower 32 bits (O2) Channel 1, 2, 3, 4, 5, 6, and 7 u[31:28], A[27:24], A[23:16], A[15:8], A[7:0] 0000 883F mS DRC1 attack Channel 1, 2, 3, 4, 5, 6, and 7 u[31:28], 1–A[27:24], 1–A[23:16], 1–A[15:8], 007F 77C0 DRC1 (1 – attack) 1–A[7:0] 0x9C 16 Channel 1, 2, 3, 4, 5, 6, and 7 u[31:28], D[27:24], D[23:16], D[15:8], D[7:0] 0000 0056 mS DRC1 decay Channel 1, 2, 3, 4, 5, 6, and 7 u[31:28], 1–D[27:24], 1–D[23:16], 1–D[15:8], 003F FFA8 DRC1 (1 – decay) 1–D[7:0] Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 75 Product Folder Links: TAS5548 |
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