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TAS5548DCAR Datasheet(PDF) 55 Page - Texas Instruments |
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TAS5548DCAR Datasheet(HTML) 55 Page - Texas Instruments |
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55 / 116 page  TAS5548 www.ti.com SLES270A – NOVEMBER 2012 – REVISED APRIL 2015 Register Maps (continued) TOTAL I2C REGISTER FIELDS DESCRIPTION OF CONTENTS DEFAULT STATE (hex) BYTES SUBADDRESS Loudness biquad coefficient b0 00FE 5045 Loudness biquad coefficient b1 0F81 AA27 0x95 20 Loudness biquad Loudness biquad coefficient b2 0000 D513 Loudness biquad coefficient a0 0000 0000 Loudness biquad coefficient a1 0FFF 2AED 0x96 4 DRC1 control Ch1–Ch7 DRC1 control Ch1–Ch7 00 00 00 00 0x97 4 DRC2 control register, Ch8 DRC2 control Ch8 00 00 00 00 Ch1–Ch7, DRC1 energy DRC1 energy 0000 883F 007F 77C0 0x98 8 Ch1–Ch7, DRC1 (1 – energy) DRC1 (1 – energy) Ch1–Ch7 DRC1 threshold DRC1 threshold (T1) – 4 bytes 0B20 E2B2 06F9 DE58 T1 0x99 8 Ch1–Ch7 DRC1 threshold DRC1 threshold (T2) – 4 bytes T2 Ch1–Ch7 , DRC1 slope k0 DRC1 slope (k0) 0040 0000 0FC0 0000 0F90 0000 0x9A 12 Ch1–Ch7, DRC1 slope k1 DRC1 slope (k1) Ch1–Ch7 DRC1 slope k2 DRC1 slope (k2) Ch1–Ch7 DRC1 offset 1 DRC1 offset 1 (O1) – 4 bytes FF82 3098 0195 B2C0 0x9B 8 Ch1–Ch7 DRC1 offset 2 DRC1 offset 2 (O2) – 4 bytes Ch1–Ch7 DRC1 attack DRC1 attack 0000 883F 007F 77C0 0000 0056 003F FFA8 Ch1–Ch7 DRC1 (1 – attack) DRC1 (1 – attack) 0x9C 16 Ch1–Ch7 DRC1 decay DRC1 decay Ch1–Ch7 DRC1 (1 – decay) DRC1 (1 – decay) Ch8 DRC2 energy DRC2 energy 0000 883F 007F 77C0 0x9D 8 Ch8 DRC2 (1 – energy) DRC2 (1 – energy) Ch8 DRC2 threshold T1 DRC2 threshold (T1) – 4 bytes 0B20 E2B2 06F9 DE58 0x9E 8 Ch8 DRC2 threshold T2 DRC2 threshold (T2) – 4 bytes Ch8 DRC2 slope k0 DRC2 slope (k0) 0040 0000 0FC0 0000 0F90 0000 0x9F 12 Ch8 DRC2 slope k1 DRC2 slope (k1) Ch8 DRC2 slope k2 DRC2 slope (k2) Ch8 DRC2 offset 1 DRC2 offset (O1) – lower 4 bytes FF82 3098 0195 B2C0 0xA0 8 Ch8 DRC2 offset 2 DRC2 offset (O2) – lower 4 bytes Ch8 DRC2 attack DRC 2 attack 0000 883F 007F 77C0 0000 0056 003F FFA8 Ch8 DRC2 (1 – attack) DRC2 (1 – attack) 0xA1 16 Ch8 DRC2 decay DRC2 decay Ch8 DRC2 (1 – decay) DRC2 (1 – decay) DRC bypass 1 Ch1 DRC1 bypass coefficient 0080 0000 0000 0000 0xA2 8 DRC inline 1 Ch1 DRC1 inline coefficient DRC bypass 2 Ch2 DRC1 bypass coefficient 0080 0000 0000 0000 0xA3 8 DRC inline 2 Ch2 DRC1 inline coefficient DRC bypass 3 Ch3 DRC1 bypass coefficient 0080 0000 0000 0000 0xA4 8 DRC inline 3 Ch3 DRC1 inline coefficient DRC bypass 4 Ch4 DRC1 bypass coefficient 0080 0000 0000 0000 0xA5 8 DRC inline 4 Ch4 DRC1 inline coefficient DRC bypass 5 Ch5 DRC1 bypass coefficient 0080 0000 0000 0000 0xA6 8 DRC inline 5 Ch5 DRC1 inline coefficient DRC bypass 6 Ch6 DRC1 bypass coefficient 0080 0000 0000 0000 0xA7 8 DRC inline 6 Ch6 DRC1 inline coefficient DRC bypass 7 Ch7 DRC1 bypass coefficient 0080 0000 0000 0000 0xA8 8 DRC inline 7 Ch7 DRC1 inline coefficient Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 55 Product Folder Links: TAS5548 |
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