| Electronic Components Datasheet Search |
|
TAS5548DCAR Datasheet(PDF) 97 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TAS5548DCAR Datasheet(HTML) 97 Page - Texas Instruments |
|
97 / 116 page ![]() CLK_Gen Control LRCK1 SCK1 SDIN1 SDIN2 8ch PWM Modulator + HP-PWMOUT 32kHz–192kHz Input 4ch ASRC Fixed 96kHz Output 32 bits Data Path 48 bits Accumulator 1365 Cycles Fixed Processing DAP 10 Channel Input Mixer 8 Channel Processing 8 Channel Output Mixer 32kHz–192kHz Input 4ch ASRC Fixed 96kHz Output Serial Audio Receiver 4ch 2 Stereo Serial Audio Receiver 4ch 2 Stereo LRCKO/LRCKIN2 SCKO/SCKIN2 SDIN3 SDIN4 4ch 4ch Serial Audio Receiver Transmitter 1 Stereo SDOUT/SDIN5 I/ O I O I I I I I I/ O I/ O MCLKO/PSVC OSC 12.288MHz 8ch O O O O O O O O O I O 2ch 2ch Bypass mode 2ch HPPWM PWM8 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 TAS5548 www.ti.com SLES270A – NOVEMBER 2012 – REVISED APRIL 2015 8.2.2 Serial Port Master/Slave Configurations The inputs to the Digital Audio Processor (DAP) come from the Asynchronous Sample Rate Converter block as follows: Figure 47. Digital Audio Signal Flow Block Diagram 8.2.2.1 Design Requirements For this design example, use the parameters listed in Table 84 as the input parameters. Table 84. Design Parameters PARAMETER VALUE Device control method Software control through I2C communication for register settings Digital Audio input Right-justified, I2S, or left-justified. Power stage Audio amplifier with PWM input 8.2.2.2 Detailed Design Procedure The DAP can feed audio data to and from the Serial Audio ports in the following manner. There are 3 main use cases: 1. Use Case 1: External Karaoke Microphone Input (ADC in on SDIN5) or External I2S Subwoofer (a) SDIN1 through 4 are slave to an external source (such as a media decoder IC). (b) A separate DOUT (for Sub) or Microphone Inout (SDIN5) needs to function at the post-ASRC rate. (c) Therefore, the device is configured to use MCLKO, SCLKO and LRCLKO. 2. Use Case 2: Mixing two different data sources (e.g. Stereo Bluetooth I2S and CD/Media Decoder (a) In an example where two different data sources need mixing, SDIN1/2 run at a different rate than SDIN3/4 (b) SCLKIN-2 and LRCLKIN-2 are used to provide an LRCLK and SCLK for the second data synchronous data source. (c) DOUT (for a wireless sub) cannot be used in this mode, as no MCLKO, SCLKO or LRCLKO are available. 3. Use Case 3: Creating an external loop for processing (e.g. using a TAS3108 or TAS3152 I2S processor) (a) SDIN1/2 run with SCLK and LRCLK as a slave. (b) SDOUT acts as a "send for external processing", in master mode, synchronized to MLCKO, SCLKO, LRCLKO Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 97 Product Folder Links: TAS5548 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |