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TAS5548DCAR Datasheet(PDF) 17 Page - Texas Instruments |
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TAS5548DCAR Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 116 page  23 22 SCLK 32Clks LRCLK LeftChannel 24-BitMode 1 19 18 20-BitMode 16-BitMode 15 14 MSB LSB 32Clks RightChannel 2-ChannelLeft-JustifiedStereoInput T0034-02 4 5 9 8 1 4 5 1 0 0 0 23 22 1 19 18 15 14 MSB LSB 4 5 9 8 1 4 5 1 0 0 0 SCLK TAS5548 www.ti.com SLES270A – NOVEMBER 2012 – REVISED APRIL 2015 Feature Description (continued) 7.3.1.2 Left-Justified Timing Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 64 fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5548 masks unused trailing data bit positions. Figure 16. Left-Justified 64-fS Format Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: TAS5548 |
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