PEB2256HT datasheet(52/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Functional Description E1/T1/J1

Data Sheet

2002-08-27

3.3

Functional Blocks

3.3.1

Microprocessor Interface

The communication between the CPU and the FALC56 is done using a set of directly

accessible registers. The interface can be configured as Intel or Motorola type with a

selectable data bus width of 8 or 16 bits.

The CPU transfers data to and from the FALC56 (through 64-byte deep FIFOs per

direction), sets the operating modes, controls function sequences, and gets status

information by writing or reading control and status registers. All accesses can be done

as byte or word accesses if enabled. If 16-bit bus width is selected, access to lower/

upper part of the data bus is determined by address line A0 and signal BHE/BLE as

shown in Table 6 and Table 7.

Table 8 shows how the ALE (Address Latch Enable) line is used to control the bus

structure and interface type. The switching of ALE allows the FALC56 to be directly

connected to a multiplexed address/data bus.

3.3.1.1

Mixed Byte/Word Access to the FIFOs

Reading from or writing to the internal FIFOs (RFIFO and XFIFO) can be done using a

8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode.

Randomly mixed byte/word access to the FIFOs is allowed without any restrictions.

Table 6

Data Bus Access (16-Bit Intel Mode)

BHE

FALC56 Data Pins Used

FIFO word access

D(15:0)

D(15:8)

D(7:0)

No transfer performed

None

Table 7

Data Bus Access (16-Bit Motorola Mode)

BLE

FALC56 Data Pins Used

FIFO word access

D(15:0)

D(7:0)

D(15:8)

No transfer performed

None

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