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PEB2256HT Datasheet(PDF) 81 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 81 Page - Infineon Technologies AG |
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81 / 490 page  FALC56 V1.2 PEB 2256 Functional Description E1 Data Sheet 81 2002-08-27 4.2.2.2 Synchronization Procedure Synchronization status is reported by bit FRS0.LFA. Framing errors are counted by the Framing Error Counter (FEC). Asynchronous state is reached after detecting 3 or 4 consecutive incorrect FAS words or 3 or 4 consecutive incorrect service words (bit 2 = 0 in time slot 0 of every other frame not containing the frame alignment word), the selection is done by bit RC0.ASY4. Additionally, the service word condition can be disabled. When the framer lost its synchronization an interrupt status bit ISR2.LFA is generated. In asynchronous state, counting of framing errors and detection of remote alarm is stopped. AIS is automatically sent to the backplane interface (can be disabled by bit FMR2.DAIS). Further on the updating of the registers RSW, RSP, RSA(8:4), RSA6S and RS(16:1) is halted (remote alarm indication, S a/Si-Bit access). The resynchronization procedure starts automatically after reaching the asynchronous state. Additionally, it can be invoked user controlled by bit FMR0.FRS (force resynchronization, the FAS word detection is interrupted until the framer is in the asynchronous state. After that, resynchronization starts automatically). Synchronous state is established after detecting: • a correct FAS word in frame n, • the presence of the correct service word (bit 2 = 1) in frame n + 1, • a correct FAS word in frame n + 2. If the service word in frame n + 1 or the FAS word in frame n + 2 or both are not found searching for the next FAS word starts in frame n + 2 just after the previous frame alignment signal. Table 17 Transmit Transparent Mode (Doubleframe E1) Transmit Transparent Source for Enabled by Framing A-Bit S a-Bits S i-Bits – XSP.TT0 TSWM.TSIF TSWM.TSIS TSWM.TRA TSWM.TSA(8:4) (int. gen.) via pin XDI 1) (int. gen.) (int. gen.) (int. gen.) (int. gen.) 1) pin XDI or XSIG or XFIFO buffer (signaling controller) XSW.XRA 2) via pin XDI XSW.XRA XSW.XRA via pin XDI XSW.XRA 2) Additionally, automatic transmission of the A-bit is selectable. XSW.XY0…4 3) via pin XDI XSW.XY0…4 XSW.XY0…4 XSW.XY0…4 via pin XDI 3) As a special extension for double frame format, the S a-bit register can be used optionally. XSW.XSIS, XSP.XSIF via pin XDI via pin XDI via pin XDI XSW.XSIS, XSP.XSIF XSW.XSIS, XSP.XSIF |
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