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PEB2256HT Datasheet(PDF) 53 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 53 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
Functional Description E1/T1/J1
Data Sheet
53
2002-08-27
The assignment of registers with even/odd addresses to the data lines in case of 16-bit
register access depends on the selected microprocessor interface mode:
Intel
(Address n + 1)
(Address n)
Motorola
(Address n)
(Address n + 1)
↑↑
↓↓
n: even address
3.3.1.2
FIFO Structure
In transmit and receive direction of the signaling controller 64-byte deep FIFOs are
provided for the intermediate storage of data between the system internal highway and
the CPU interface. The FIFOs are divided into two halves of 32 bytes. Only one half is
accessible to the CPU at any time.
In case 16-bit data bus width is selected by fixing pin DBW to logical 1 word access to
the FIFOs is enabled. Data output to bus lines D(15:0) as a function of the selected
interface mode is shown in Figure 8 and Figure 9. Of course, byte access is also
allowed. The effective length of the accessible part of RFIFO can be changed from
32 bytes (reset value) down to 2 bytes.
Table 8
Selectable Bus and Microprocessor Interface Configuration
ALE
IM
Microprocessor interface
Bus Structure
V
SS/VDD
1
Motorola
de-multiplexed
V
SS/VDD
0
Intel
de-multiplexed
switching
0
Intel
multiplexed
Data Lines
D15
D8
D7
D0



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