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PEB2256HT Datasheet(PDF) 21 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 21 Page - Infineon Technologies AG |
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21 / 490 page  FALC56 V1.2 PEB 2256 Introduction Data Sheet 21 2002-08-27 • Channel loop back, line loop back or payload loop back capabilities (TR54016) • Pseudo-random binary sequence generator and monitor (framed or unframed) • Clear channel capabilities (T1/J1) • Loop-timed mode Signaling Controller • Three HDLC controllers Bit stuffing, CRC check and generation, flag generation, flag and address recognition, handling of bit oriented functions • Supports signaling system #7 delimitation, alignment and error detection according to ITU-Q.703 processing of fill in signaling units, processing of errored signaling units • CAS/CAS-BR controller with last look capability, enhanced CAS-register access and freeze signaling indication • DL-channel protocol for ESF format according to ANSI T1.403 specification or according to AT&T TR54016 (T1/J1) • DL-bit access for F72 (SLC96) format (T1/J1) • Generates periodical performance report according to ANSI T1. 403 • Provides access to serial signaling data streams • Multiframe synchronization and synthesis according to ITU-T G.732 • Alarm insertion and detection (AIS and LOS in time slot 16) • Transparent mode • FIFO buffers (64 bytes deep) for efficient transfer of data packets • Time slot assignment Any combination of time slots selectable for data transfer independent of signaling mode (useful for fractional T1/J1 applications) • Time-slot 0 S a8...4-bit handling via FIFOs (E1) • HDLC access to any S a-bit combination (E1) Microprocessor Interface • 8/16-bit microprocessor bus interface (Intel or Motorola type) • All registers directly accessible (byte or word access) • Multiplexed and non-multiplexed address bus operations • Hard/software reset options • Extended interrupt capabilities • One-second timer (internal or external timing reference) |
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