PEB2256HT datasheet(58/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Functional Description E1/T1/J1

Data Sheet

2002-08-27

If no boundary scan operation is used, TRS has to be connected to RST or V

SS. TMS,

TCK and TDI do not need to be connected since pullup transistors ensure high input

levels in this case.

Test handling (boundary scan operation) is performed using the pins TCK (Test Clock),

TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output) when the

TAP controller is not in its reset state, that means TRS is connected to V

DD or it remains

unconnected due to its internal pull up. Test data at TDI is loaded with a clock signal

connected to TCK. "1" or "0" on TMS causes a transition from one controller state to

another; constant "1" on TMS leads to normal operation of the chip.

An input pin (I) uses one boundary scan cell (data in), an output pin (O) uses two cells

(data out and enable) and an I/O-pin (I/O) uses three cells (data in, data out and enable).

Note that most functional output and input pins of the FALC56 are tested as I/O pins in

boundary scan, hence using three cells. The desired test mode is selected by serially

loading a 8-bit instruction code into the instruction register through TDI (LSB first).

EXTEST is used to examine the interconnection of the devices on the board. In this test

mode at first all input pins capture the current level on the corresponding external

interconnection line, whereas all output pins are held at constant values ("0" or "1"). Then

the contents of the boundary scan is shifted to TDO. At the same time the next scan

vector is loaded from TDI. Subsequently all output pins are updated according to the new

boundary scan contents and all input pins again capture the current external level

afterwards, and so on.

SAMPLE is a test mode which provides a snapshot of pin levels during normal operation.

IDCODE: A 32-bit identification register is serially read out on pin TDO. It contains the

version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits).

The LSB is fixed to "1".

The ID code field is set to: 0001 0000 0000 0101 1001 0000 1000 0011

Version = 3

H, Part Number = 0059H, Manufacturer = 083H (including LSB, fixed to "1")

BYPASS: A bit entering TDI is shifted to TDO after one TCK clock cycle.

An alphabetical overview of all TAP controller operation codes is given in Table 9.

Table 9

TAP Controller Instruction Codes

TAP Instruction

Instruction Code

BYPASS

11111111

EXTEST

00000000

IDCODE

00000100

SAMPLE

00000001

reserved for device test

01010011

PEB2256HT Datasheet(PDF) 58 Page - Infineon Technologies AG

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