PEB2256HT datasheet(56/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Functional Description E1/T1/J1

Data Sheet

2002-08-27

interrupt source register. After reading the assigned interrupt status registers ISR(5:0),

the pointer in register GIS is cleared or updated if another interrupt requires service.

If all pending interrupts are acknowledged by reading (GIS is reset), pin INT goes

inactive.

Updating of interrupt status registers ISR(5:0) and GIS is only prohibited during read

access.

Masked Interrupts Visible in Status Registers

• The Global Interrupt Status register (GIS) indicates those interrupt status registers

with active interrupt indications (GIS.ISR(5:0)).

• An additional mode can be selected via bit GCR.VIS.

• In this mode, masked interrupt status bits neither generate an interrupt on pin INT nor

are they visible in GIS, but are displayed in the corresponding interrupt status

This mode is useful when some interrupt status bits are to be polled in the individual

interrupt status registers.

Note: In the visible mode, all active interrupt status bits, whether the corresponding

actual interrupt is masked or not, are reset when the interrupt status register is

read. Thus, when polling of some interrupt status bits is desired, care must be

taken that unmasked interrupts are not lost in the process.

Note: All unmasked interrupt statuses are treated as before.

Please note that whenever polling is used, all interrupt status registers concerned have

to be polled individually (no “hierarchical” polling possible), since GIS only contains

information on actually generated, i.e. unmasked interrupts.

PEB2256HT Datasheet(PDF) 56 Page - Infineon Technologies AG