PEB2256HT datasheet(66/490 Pages) INFINEON

66 / 490 page

FALC56 V1.2

PEB 2256

Functional Description E1

Data Sheet

2002-08-27

bits LIM1.RIL(2:0) (see Chapter 11.3 on page 447). The number N can be set by an

8-bit register (PCD). The contents of the PCD register is multiplied by 16, which results

in the number of pulse periods, i.e. the time which has to suspend until the alarm has

to be detected. The programmable range is 16 to 4096 pulse periods. ETS300233

requires detection intervals of at least 1 ms. This time period results always in a LFA

(Loss of Frame Alignment) before a LOS is detected.

• Recovery:

In general the recovery procedure starts after detecting a logical one (digital receive

interface) or a pulse (analog receive interface) with an amplitude more than Q dB

(defined by LIM1.RIL(2:0)) of the nominal pulse. The value in the 8-bit register PCR

defines the number of pulses (1 to 255) to clear the LOS alarm.

If a loss-of-signal condition is detected in long-haul mode, the data stream can optionally

be cleared automatically to avoid bit errors before LOS is indicated. The selection is

done by LIM1.CLOS = 1.

4.1.9

Receive Jitter Attenuator (E1)

The receive jitter attenuator is placed in the receive path. The working clock is an

internally generated high frequency clock based on the clock provided on pin MCLK. The

jitter attenuator meets the requirements of ITU-T I.431, G. 736 to 739, G.823 and ETSI

TBR12/13.

The internal PLL circuitry DCO-R generates a "jitter-free" output clock which is directly

dependent on the phase difference of the incoming clock and the jitter attenuated

clock.The receive jitter attenuator can be synchronized either on the extracted receive

clock RCLK or on a 2.048-MHz/8-kHz clock provided on pin SYNC (8 kHz in master

mode only). The received data is written into the receive elastic buffer with RCLK and

are read out with the de-jittered clock sourced by DCO-R. The jitter attenuated clock can

be output on pins RCLK, CLK1 or SCLKR. Optionally an 8-kHz clock is provided on pin

SEC

⁄FSC.

The DCO-R circuitry attenuates the incoming jittered clock starting at 2-Hz jitter

frequency with 20 dB per decade fall-off. Wander with a jitter frequency below 2 Hz is

passed unattenuated. The intrinsic jitter in the absence of any input jitter is < 0.02 UI.

For some applications it might be useful starting of jitter attenuation at lower frequencies.

Therefore the corner frequency is switchable by the factor of ten down to 0.2 Hz

(LIM2.SCF).

The DCO-R circuitry is automatically centered to the nominal bit rate if the reference

clock on pin SYNC/RCLK is missed for 2, 3 or 4 of the 2.048-MHz clock periods. This

center function of DCO-R can be disabled (CMR2.DCF = 1) in order to accept a gapped

reference clock. In analog line interface mode RCLK is always running. Only in digital

line interface mode with single-rail data a gapped clock can occur.

The receive jitter attenuator works in two different modes:

PEB2256HT Datasheet(PDF) 66 Page - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 66 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL