PEB2256HT datasheet(100/490 Pages) INFINEON

100 / 490 page

FALC56 V1.2

PEB 2256

Functional Description E1

Data Sheet

100

2002-08-27

4.4.7.2

Support of Signaling System #7

The HDLC controller of channel 1 supports the signaling system #7 (SS7) which is

described in ITU-Q.703. The following description assumes, that the reader is familiar

with the SS7 protocol definition.

SS7 support must be activated by setting the MODE register. Data stored in the transmit

FIFO (XFIFO) is sent automatically. The SS7 protocol is supported by the following

hardware features in transmit direction:

• transmission of flags at the beginning of each Signaling Unit

• bit stuffing (zero insertion)

• calculation of the CRC16 checksum:

The transmitter adds the checksum to each Signaling Unit.

Each Signaling Unit written to the transmit FIFO (XFIFO, 2

×32 bytes) is sent once or

repeatedly including flags, CRC checksum and stuffed bits. After e.g. an MSU has been

transmitted completely, the FALC56 optionally starts sending of FISUs containing the

forward sequence number (FSN) and the backward sequence number (BSN) of the

previously transmitted Signaling Unit. Setting bit CCR5.AFX causes Fill In Signaling

Units (FISUs) to be sent continuously, if no HDLC or Signaling Unit (SU) is to be

transmitted from XFIFO. During update of XFIFO, automatic transmission is interrupted

and resumed after update is completed. The internally generated FISUs contain FSN

and BSN of the last transmitted Signaling Unit written to XFIFO.

Using CMDR.XREP = 1, the contents of XFIFO can be sent continuously. Clearing of

CMDR.XRES/SRES stops the automatic repetition of transmission. This function is also

available for HDLC frames, so no flag generation, CRC byte generation and bit stuffing

is necessary.

Example: After an MSU has been sent repetitively and XREP has been cleared, FISUs

are sent automatically.

4.4.7.3

a-Bit Access (E1)

The FALC56 supports the S

a-bit signaling of time slot 0 of every other frame as follows:

• the access through register XSW

• the access through registers XSA(8:4), capable of storing the information for a

complete multiframe

• the access through the 64 byte deep XFIFO of the signaling controller (HDLC channel

1 only)

This S

a-bit access gives the opportunity to transparent a bit stream as well as HDLC

frames where the signaling controller automatically processes the HDLC protocol. Any

combination of S

a-bits which shall be inserted in the outgoing data stream can be

selected by XC0.SA(8:4).

PEB2256HT Datasheet(PDF) 100 Page - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 100 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL