PEB2256HT datasheet(57/490 Pages) INFINEON

Part #	PEB2256HT

Description	E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PDF	490 Pages

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Manufacturer	INFINEON [Infineon Technologies AG]

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FALC56 V1.2

PEB 2256

Functional Description E1/T1/J1

Data Sheet

2002-08-27

3.3.2

Boundary Scan Interface

In the FALC56 a Test Access Port (TAP) controller is implemented. The essential part

of the TAP is a finite state machine (16 states) controlling the different operational modes

of the boundary scan. Both, TAP controller and boundary scan, meet the requirements

given by the JTAG standard IEEE 1149.1. Figure 11 gives an overview.

Figure 11

Block Diagram of Test Access Port and Boundary Scan

After switching on the device (power-on), a reset signal has to be applied to TRS, which

forces the TAP controller into test logic reset state.

For normal operation without boundary scan access, the boundary reset pin TRS can be

tied to the device reset pin RES.

The boundary length is 129.

F0115

TRS

TCK

TMS

TDI

TDO

clock

test

control

data in

enable

data

out

Clock

Generation

Reset

TAP Controller

finite state machine

instruction register

test signal generator

TAP controller reset

control

bus

BD data in

BD data out

ID data out

PEB2256HT Datasheet(PDF) 57 Page - Infineon Technologies AG

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