PEB2256HT datasheet(61/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Functional Description E1

Data Sheet

2002-08-27

4.1.3

Receive Equalization Network (E1)

The FALC56 automatically recovers the signals received on pins RL1/2 in a range of up

to -43 dB. The maximum reachable length with a 22 AWG twisted pair cable is 1500 m.

After reset the FALC56 is in short-haul“ mode, received signals are recovered up to -10

dB of cable attenuation. Switching in Long-haul“ mode is done by setting of bit

LIM0.EQON.

The integrated receive equalization network recovers signals with up to -43 dB of cable

attenuation. Noise filters eliminate the higher frequency part of the received signals. The

incoming data is peak-detected and sliced to produce the digital data stream. The slicing

level is software selectable in four steps (45%, 50%, 55%, 67%). For typical E1

applications, a level of 50% is used. The received data is then forwarded to the clock &

data recovery unit.

In long-haul mode, the current equalizer status is indicated by register RES (Receive

Equalizer Status).

4.1.4

Receive Line Attenuation Indication (E1)

Status register RES reports the current receive line attenuation in a range from 0 to -43

dB in 25 steps of approximately 1.7 dB each. The least significant 5 bits of this register

indicate the cable attenuation in dB. These 5 bits are only valid in combination with the

most significant two bits (RES.EV1/0 = 01).

4.1.5

Receive Clock and Data Recovery (E1)

The analog received signal on port RL1/2 is equalized and then peak-detected to

produce a digital signal. The digital received signal on port RDIP/N is directly forwarded

to the DPLL. The receive clock and data recovery extracts the route clock from the data

stream received at the RL1/2, RDIP/RDIN or ROID lines and converts the data stream

into a single-rail, unipolar bit stream. The clock and data recovery uses an internally

generated high frequency clock based on MCLK.

The recovered route clock or a de-jittered clock can be output on pin RCLK as shown in

Table 10.

See also Table 13 on page 67 for details of master/slave clocking.

PEB2256HT Datasheet(PDF) 61 Page - Infineon Technologies AG