PEB2256HT datasheet(82/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Functional Description E1

Data Sheet

2002-08-27

Reaching the synchronous state causes a frame alignment recovery interrupt status

ISR2.FAR if enabled. Undisturbed operation starts with the beginning of the next

doubleframe.

4.2.2.3

A-Bit Access

If the FALC56 detects a remote alarm indication in the received data stream the interrupt

status bit ISR2.RA is set. With setting of bit XSW.XRA a remote alarm (RAI) is sent to

the far end.

By setting FMR2.AXRA the FALC56 automatically transmit the remote alarm bit = 1 in

the outgoing data stream if the receiver detects a loss of frame alignment FRS0.LFA = 1.

If the receiver is in synchronous state FRS0.LFA = 0 the remote alarm bit is reset.

Note: The A-bit can be processed by the system interface. Setting bit TSWM.TRA

enables transparency for the A-bit in transmit direction (refer to Table 16).

4.2.2.4

a-Bit Access

As an extension for access to the S

a-bits through registers RSA(8:4)/XSA(8:4) an option

is implemented to allow the usage of internal S

a-bit registers RSA(8:4)/XSA(8:4) in

doubleframe format.

This function is enabled by setting FMR1.ENSA = 1 for the transmitter and

FMR1.RFS(1:0) = 01 for the receiver. In this case the FALC56 internally works with a 16-

frame structure but no CRC multiframe alignment/generation is performed.

PEB2256HT Datasheet(PDF) 82 Page - Infineon Technologies AG