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PEB2256HT Datasheet(PDF) 97 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 97 Page - Infineon Technologies AG |
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97 / 490 page ![]() FALC56 V1.2 PEB 2256 Functional Description E1 Data Sheet 97 2002-08-27 Figure 24 Transmit Clock System (E1) Note: DR = Dual-Rail interface DCO-X Digital Controlled Oscillator transmit 4.4.4 Transmit Elastic Buffer (E1) The received bit stream from pin XDI is optionally stored in the transmit elastic buffer. The memory is organized as the receive elastic buffer. The functions are also equal to the receive side. Programming of the transmit buffer size is done by SIC1.XBS1/0: • XBS1/0 = 00: Bypass of the transmit elastic buffer • XBS1/0 = 01: one frame buffer or 256 bits Maximum of wander amplitude (peak-to-peak): 100 UI (1 UI = 488 ns) average delay after performing a slip: 128 bits • XBS1/0 = 10: two frame buffer or 512 bits Maximum of wander amplitude: 190 UI average delay after performing a slip: 1 frame or 256 bits • XBS1/0 = 11: short buffer or 92 bits: Maximum of wander amplitude: 18 us average delay after performing a slip: 46 bits The functions of the transmit buffer are: ITS10305 Pulse Shaper D Jitter Framer SCLKX XL1/ XDOP/ XL2/ XDON XCLK A XOID DR DR Elastic Store XDI RCLK TCLK Transmit Attenuator DCO-X SCLKR Internal Clock of Receive System TCLK ÷ 4 Clocking Unit MCLK (E1: 8MHz) Interface Transmit (T1: 6MHz) E1: 8MHz T1: 6MHz |
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