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PEB2256HT Datasheet(PDF) 80 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 80 Page - Infineon Technologies AG |
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80 / 490 page ![]() FALC56 V1.2 PEB 2256 Functional Description E1 Data Sheet 80 2002-08-27 4.2.2 Doubleframe Format (E1) The framing structure is defined by the contents of time slot 0 (refer to Table 16). 4.2.2.1 Transmit Transparent Modes In transmit direction, contents of time slot 0 frame alignment signal of the outgoing PCM frame are normally generated by the FALC56. However, transparency for the complete time slot 0 can be achieved by selecting the transparent mode XSP.TT0. With the Transparent Service Word Mask register TSWM the S i-bits, A-bit and the Sa-bits can be selectively switched through transparently. Table 16 Allocation of Bits 1 to 8 of Time Slot 0 (E1) Bit AlternateNumber Frames 12 3 456 78 Frame Containing the Frame Alignment Signal S i 0 0 110 11 Note 1) Frame Alignment Signal Frame not Containing the Frame Alignment Signal or Service Word S i 1A S a4 S a5 S a6 S a7 S a8 Note 1) 1) S i-bits: reserved for international use. If not used, these bits should be fixed to "1". Access to received information trough bits RSW.RSI and RSP.RSIF. Transmission is enabled by bits XSW.XSIS and XSP.XSIF. Note 2) 2) Fixed to "1". Used for synchronization. Note 3) 3) Remote alarm indication: In undisturbed operation "0"; in alarm condition "1". Note 4) 4) Sa-bits: Reserved for national use. If not used, they should be fixed at "1". Access to received information trough bits RSW.RY0…4. Transmission is enabled by bits XSW.XY0…4. HDLC signaling in bits S a4 to 8 is selectable. As a special extension for double frame format, the S a-bit registers RSA4 to 8/XSA4 to 8 can be used optionally. |
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