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AD6679

Data Sheet

Rev. B | Page 40 of 81

DIGITAL DOWNCONVERTER (DDC)

The AD6679 includes four digital downconverters (DDCs) that

provide filtering and reduce the output data rate. This digital

processing section includes an NCO, up to four half-band

decimating filter, a finite impulse response (FIR) filter, a gain

stage, and a complex to real conversion stage. Each of these

processing blocks has control lines that allow it to be

independently enabled and disabled to provide the desired

processing function. The DDC can be configured to output

either real data or complex output data.

DDC I/Q INPUT SELECTION

The AD6679 has two ADC channels and four DDC channels.

Each DDC channel has two input ports that can be paired to

support both real and complex inputs through the I/Q crossbar

mux. For real signals, both DDC input ports must select the

same ADC channel (that is, DDC Input Port I = ADC Channel A

and DDC Input Port Q = ADC Channel A). For complex signals,

each DDC input port must select different ADC channels (that

is, DDC Input Port I = ADC Channel A and DDC Input Port Q

= ADC Channel B).

The inputs to each DDC are controlled by the DDC input selec-

tion registers (Register 0x311, Register 0x331, Register 0x351, and

configure the DDCs.

DDC I/Q OUTPUT SELECTION

Each DDC channel has two output ports that can be paired to

support both real and complex outputs. For real output signals,

only the DDC Output Port I is used (the DDC Output Port Q is

invalid). For complex I/Q output signals, both DDC Output

Port I and DDC Output Port Q are used.

The I/Q outputs to each DDC channel are controlled by the

DDC complex to real enable bit, Bit 3, in the DDC control

registers (Register 0x310, Register 0x330, Register 0x350, and

The Chip Q ignore bit in the chip mode register (Register 0x200,

Bit 5) controls the chip output muxing of all the DDC channels.

When all DDC channels use real outputs, set this bit high to

ignore all DDC Q output ports. When any of the DDC channels

are set to use complex I/Q outputs, the user must clear this bit

to use both DDC Output Port I and DDC Output Port Q. For

more information, see Figure 71.

DDC GENERAL DESCRIPTION

The four DDC blocks extract a portion of the full digital

spectrum captured by the ADC(s). They are intended for IF

sampling or oversampled baseband radios requiring wide

bandwidth input signals.

Each DDC block contains the following signal processing

stages:



Frequency translation stage (optional)



Filtering stage



Gain stage (optional)



Complex to real conversion stage (optional)

Frequency Translation Stage (Optional)

This stage consists of a 12-bit complex NCO and quadrature

mixers that can be used for frequency translation of both real

and complex input signals. This stage shifts a portion of the

available digital spectrum down to baseband.

Filtering Stage

After shifting down to baseband, this stage decimates the

frequency spectrum using a chain of up to four half-band low-

pass filters for rate conversion. The decimation process lowers

the output data rate, which, in turn, reduces the output interface

rate.

Gain Stage (Optional)

Due to losses associated with mixing a real input signal down to

baseband, this stage compensates by adding an additional 0 dB

or 6 dB of gain.

Complex to Real Conversion Stage (Optional)

When real outputs are necessary, this stage converts the

complex outputs back to real outputs by performing an fS/4

mixing operation together with a filter to remove the complex

component of the signal.

Figure 63 shows the detailed block diagram of the DDCs

implemented in the AD6679.

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