AD6679 datasheet(68/81 Pages) AD

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AD6679

Data Sheet

Rev. B | Page 68 of 81

SERIAL PORT INTERFACE (SPI)

The AD6679 SPI allows the user to configure the converter for

specific functions or operations through a structured register

space provided inside the ADC. The SPI gives the user added

flexibility and customization, depending on the application.

Addresses are accessed via the serial port and can be written to

or read from via the serial port. Memory is organized into bytes

that can be further divided into fields. These fields are docu-

mented in the Memory Map section. For detailed operational

information, see the Serial Control Interface Standard.

CONFIGURATION USING THE SPI

Three pins define the SPI of this ADC: the SCLK pin, the SDIO

pin, and the CSB pin (see Table 39). The SCLK (serial clock) pin is

used to synchronize the read and write data presented from/to the

ADC. The SDIO (serial data input/output) pin is a dual-purpose

pin that allows data to be sent to and read from the internal

ADC memory map registers. The CSB (chip select bar) pin is an

active low control that enables or disables the read and write

cycles.

Table 39. Serial Port Interface Pins

Function

SCLK

Serial clock. The serial shift clock input, which

synchronizes serial interface reads and writes.

SDIO

Serial data input/output. A dual-purpose pin that

typically serves as an input or an output, depending on

the instruction being sent and the relative position in the

timing frame.

CSB

Chip select bar. An active low control that gates the read

and write cycles.

The falling edge of CSB, in conjunction with the rising edge of

SCLK, determines the start of the framing. See Figure 3 and

Table 5 for an example of the serial timing and its definitions.

Other modes involving the CSB pin are available. The CSB pin

can be held low indefinitely, which permanently enables the

device; this is called streaming. The CSB pin can stall high

between bytes to allow additional external timing. When CSB is

tied high, SPI functions are placed in a high impedance mode.

This mode turns on any SPI pin secondary functions.

All data is composed of 8-bit words. The first bit of each

individual byte of serial data indicates whether a read or write

command is issued. This bit allows the SDIO pin to change

direction from an input to an output.

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to be used both to program the chip and to read

the contents of the on-chip memory. If the instruction is a readback

operation, performing a readback causes the SDIO pin to change

direction from an input to an output at the appropriate point in

the serial frame.

Data can be sent in MSB first mode or in LSB first mode. MSB

first is the default configuration on power-up and can be

changed via the SPI port configuration register. For more

information about this and other features, see the Serial Control

Interface Standard.

HARDWARE INTERFACE

The pins described in Table 39 compose the physical interface

between the user programming device and the serial port of the

AD6679. The SCLK pin and the CSB pin function as inputs

when using the SPI. The SDIO pin is bidirectional, functioning

as an input during write phases and as an output during

readback.

The SPI is flexible enough to be controlled by either FPGAs or

microcontrollers. One method for SPI configuration is described

in detail in the AN-812 Application Note, Microcontroller-

Based Serial Port Interface (SPI) Boot Circuit.

Do not activate the SPI port during periods when the full

dynamic performance of the converter is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade converter performance. If the on-board SPI bus is used

for other devices, it may be necessary to provide buffers between

this bus and the AD6679 to prevent these signals from

transitioning at the converter inputs during critical sampling

periods.

SPI ACCESSIBLE FEATURES

Table 40 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in the Serial Control Interface Standard. The AD6679 device

specific features are described in the Memory Map section.

Table 40. Features Accessible Using the SPI

Feature Name

Description

Mode

Allows the user to set either power-down mode or standby mode

Clock

Allows the user to access the clock divider via the SPI

Test Input/Output

Allows the user to set test modes to have known data on output bits

Output Mode

Allows the user to set up outputs

Serializer/Deserializer (SERDES) Output Setup

Allows the user to vary SERDES settings, including swing and emphasis

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