AD6679 datasheet(31/81 Pages) AD

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Data Sheet

AD6679

Rev. B | Page 31 of 81

Input Common Mode

The analog inputs of the AD6679 are internally biased to the

common mode, as shown in Figure 45. The common-mode

buffer has a limited range in that the performance suffers

greatly if the common-mode voltage drops by more than

100 mV. Therefore, in dc-coupled applications, set the

common-mode voltage to 2.05 V ± 100 mV to ensure proper

ADC operation.

Analog Input Controls and SFDR Optimization

The AD6679 offers flexible controls for the analog inputs such

as input termination, buffer current, and input full-scale

adjustment. All of the available controls are shown in Figure 45.

AIN CONTROL

(SPI) REGISTERS

(REG 0x008, REG 0x015,

REG 0x016, REG 0x018,

REG 0x025)

10pF

VIN+x

VIN–x

AVDD3

VCM

BUFFER

400Ω

3pF

Figure 45. Analog Input Controls

Use Register 0x018, Register 0x019, Register 0x01A, Register 0x11A,

each channel to optimize the SFDR over various input frequencies

and bandwidths of interest.

Input Buffer Control Registers (Register 0x018,

The input buffer has many registers that set the bias currents

and other settings for operation at different frequencies. These

bias currents and settings can be changed to suit the input

frequency range of operation. Register 0x018 controls the buffer

bias current to reduce the effects of charge kickback from the

ADC core. This setting can be scaled from a low setting of 1.0× to

a high setting of 8.5×. The default setting in Register 0x018 is

2.0×. These settings are sufficient for operation in the first

Nyquist zone. As the input buffer currents are set, the amount

of current required by the AVDD3 supply changes. This

relationship is shown in Figure 46. For a complete list of buffer

current settings, see Table 41.

110

130

150

170

190

210

230

250

1.5×

2.5×

3.5×

4.5×

5.5×

6.5×

7.5×

8.5×

BUFFER CURRENT SETTING

Figure 46. Typical IAVDD3 vs. Buffer Current Setting in Register 0x018

offer secondary bias controls for the input buffer for frequencies

>500 MHz. Use Register 0x934 to reduce input capacitance to

achieve wider signal bandwidth but doing so may result in

slightly lower linearity and noise performance. These register

settings do not affect the AVDD3 power as much as Register 0x018

does. For frequencies <500 MHz, it is recommended to use the

default settings for these registers. Table 11 shows the recom-

mended values for the buffer current control registers for various

speed grades.

zones (>1000 MHz) but is not necessary. Using Register 0x11A

can help the ADC sampling network to optimize the sampling

and settling times internal to the ADC for high frequency opera-

tion. For frequencies greater than 500 MHz, it is recommended

to operate the ADC core at a 1.46 V full-scale setting. This setting

offers better SFDR without any significant decrease in SNR.

Figure 47, Figure 48, and Figure 49 show the SFDR vs. input

frequency for various buffer settings for the AD6679. The

recommended settings shown in Table 11 were used to collect

the data while changing the contents of register 0x018 only.

100

150

200

250

300

1.0×

1.5×

2.0×

3.0×

350

400

450

500

INPUT FREQUENCY (MHz)

4.5×

Figure 47. Buffer Current Sweeps (SFDR vs. Input Frequency and IBUFF);

10 MHz < fIN < 500 MHz; Front-End Network Shown in Figure 43

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