AD6679 datasheet(32/81 Pages) AD

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AD6679

Data Sheet

Rev. B | Page 32 of 81

500

550

600

650

700

750

800

850

900

950

1000

INPUT FREQUENCY (MHz)

4.5×

5.0×

6.0×

7.0×

8.0×

Figure 48. Buffer Current Sweeps (SFDR vs. Input Frequency and IBUFF);

500 MHz < fIN < 1000 MHz; Front-End Network Shown in Figure 44

1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000

INPUT FREQUENCY (MHz)

4.5×

5.0×

6.0×

7.0×

8.0×

Figure 49. Buffer Current Sweeps (SFDR vs. Input Frequency and IBUFF);

1 GHz < fIN < 2 GHz; Front-End Network Shown in Figure 44

Absolute Maximum Input Swing

The absolute maximum input swing allowed at the inputs of the

AD6679 is 4.3 V p-p differential. Signals operating near or at

this level can cause permanent damage to the ADC.

VOLTAGE REFERENCE

A stable and accurate 1.0 V voltage reference is built into the

AD6679. This internal 1.0 V reference sets the full-scale input

range of the ADC. The full-scale input range can be adjusted via

swing, see Table 41. Figure 50 shows the block diagram of the

internal 1.0 V reference controls.

ADC

CORE

FULL-SCALE

VOLTAGE

ADJUST

V_1P0 PIN

CONTROL SPI

(REG 0x025 AND

REG 0x024)

V_1P0

VIN–A/

VIN–B

VIN+A/

VIN+B

INTERNAL

V_1P0

GENERATOR

INPUT FULL-SCALE

RANGE ADJUST

SPI REGISTER

(REG 0x025 AND REG 0x024)

Figure 50. Internal Reference Configuration and Controls

Table 11. SFDR Optimization for Input Frequencies

Frequency

Buffer

Control 1

(Register

0x018)

Buffer

Control 2

(Register

0x019)

Buffer

Control 3

(Register

0x01A)

Buffer

Control 4

(Register

0x11A)

Buffer

Control 5

(Register

0x935)

Input Full-

Scale

Range

(Register

0x025)

Input Full-

Scale

Control

(Register

0x030)

Input

Capacitance

(Register

0x934)

Input

Termination

(Register

0x016)1

DC to 250 MHz

0x20

(2.0×)

0x60

(Setting 3)

0x0A

(Setting 3)

0x00 (off)

0x04 (on)

0x0C

(2.06 V p-p)

0x04

0x1F

0x0C/0x1C/0x6C

250 MHz to

500 MHz

0x70

(4.5×)

0x60

(Setting 3)

0x0A

(Setting 3)

0x00 (off)

0x04 (on)

0x0C

(2.06 V p-p)

0x04

0x1F

0x0C/0x1C/0x6C

500 MHz to

1 GHz

0x80

(5.0×)

0x40

(Setting 1)

0x08

(Setting 1)

0x00 (off)

0x08

(1.46 V p-p)

0x18

0x1F/0x002

0x0C/0x1C/0x6C

1 GHz to 2 GHz

0xF0

(8.5×)

0x40

(Setting 1)

0x08

(Setting 1)

0x00 (off)

0x08

(1.46 V p-p)

0x18

0x1F/0x002

0x0C/0x1C/0x6C

The input termination can be changed to accommodate the application with little or no impact to ac performance.

The input capacitance can be set to 1.5 pF to achieve wider input bandwidth but doing so results in slightly lower ac performance.

AD6679 Datasheet(PDF) 32 Page - Analog Devices

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