AD6679 datasheet(24/81 Pages) AD

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AD6679

Data Sheet

Rev. B | Page 24 of 81

Pin No.

Mnemonic

Type

Description

CMOS Outputs

J14, J1

FD_A, FD_B

Output

Fast Detect Outputs for Channel A and Channel B.

Digital Inputs

C7, C8

SYNC+,

SYNC−

Input

Active High LVDS Sync Input—True/Complement.

Data Outputs

N4, P4

DATA0−,

DATA0+

Output

LVDS Byte Data 0—Complement/True.

N5, P5

DATA1−,

DATA1+

Output

LVDS Byte Data 1—Complement/True.

N9, P9

DATA2−,

DATA2+

Output

LVDS Byte Data 2—Complement/True.

N10, P10

DATA3−,

DATA3+

Output

LVDS Byte Data 3—Complement/True.

N11, P11

DATA4−,

DATA4+

Output

LVDS Byte Data 4—Complement/True.

N12, P12

DATA5−,

DATA5+

Output

LVDS Byte Data 5—Complement/True.

N13, P13

DATA6−,

DATA6+

Output

LVDS Byte Data 6—Complement/True.

N14, P14

DATA7−,

DATA7+

Output

LVDS Byte Data 7—Complement/True.

M13, M14

STATUS−,

STATUS+

Output

LVDS Status Output Data—Complement/True.

L13, L14

FCO−, FCO+

Output

LVDS Frame Clock Output Data—Complement/True.

K13, K14

DCO−,

DCO+

Output

LVDS Digital Clock Output Data—Complement/True.

DUT Controls

SDIO

Input/output

SPI Serial Data Input/Output.

SCLK

Input

SPI Serial Clock.

CSB

Input

SPI Chip Select (Active Low).

J13

PDWN/STBY

Input

Power-Down Input (Active High). The operation of this

pin depends on the SPI mode and can be configured in

power-down or standby mode.

No Connects

M1, M2, N1 to N3, N6, P1 to P3, P6

DNC

Do Not Connect. Do not connect to these pins.

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