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AD6679

Data Sheet

Rev. B | Page 34 of 81

Input Clock Divider

The AD6679 contains an input clock divider with the ability to

divide the Nyquist input clock by 1, 2, 4, or 8. The divide ratio

can be selected using Register 0x10B. This is shown in Figure 56.

The maximum frequency at the output of the divider is 500 MHz.

The maximum frequency at the CLK± inputs is 4 GHz. This is

the limit of the divider. In applications where the clock input is

a multiple of the sample clock, take care to program the

appropriate divider ratio into the clock divider before applying

the clock signal. This ensures that the current transients during

device startup are controlled.

CLK+

CLK–

÷2

÷4

REG 0x10B

÷8

Figure 56. Clock Divider Circuit

The AD6679 clock divider can be synchronized using the

external SYNC± input. A valid SYNC± input causes the clock

divider to reset to a programmable state. This feature is enabled

by setting Bit 7 of Register 0x10D. This synchronization feature

allows multiple devices to have their clock dividers aligned to

guarantee simultaneous input sampling.

After programming the desired clock divider settings, changing

the input clock frequency or glitching the input clock a datapath

soft reset is recommended by writing 0x02 to Register 0x001.

This reset function restarts all the datapath and clock generation

circuitry in the device. The reset occurs on the first clock cycle

after the register is programmed, and the device requires 5 ms

to recover. This reset does not affect the contents of the memory

map registers.

Input Clock Divider ½ Period Delay Adjustment

The input clock divider inside the AD6679 provides phase delay

in increments of ½ the input clock cycle. Program Register 0x10C

to enable this delay independently for each channel.

Clock Fine Delay Adjustment

To adjust the AD6679 sampling edge instant, write to Register

0x117 and Register 0x118. Setting Bit 0 of Register 0x117 enables

the fine delay feature, and Register 0x118, Bits[7:0], set the value

of the delay. This value can be programmed individually for each

channel. The clock delay can be adjusted from −151.7 ps to

+150 ps in ~1.7 ps increments. The clock delay adjustment

takes effect immediately when it is enabled via SPI writes.

Enabling the clock fine delay adjustment in Register 0x117

causes a datapath reset.

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency

(fA) due only to aperture jitter (tJ) is calculated by

SNR = 20 × log10(2 × π × fA × tJ)

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter specifications. IF undersampling

applications are particularly sensitive to jitter (see Figure 57).

100

1000

100

110

120

130

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

10 BITS

16 BITS

14 BITS

12 BITS

8 BITS

RMS CLOCK JITTER REQUIREMENT

ANALOG INPUT FREQUENCY (MHz)

Figure 57. Ideal SNR vs. Analog Input Frequency and Jitter

Treat the clock input as an analog signal when aperture jitter

may affect the dynamic range of the AD6679. Separate the power

supplies for the clock drivers from the ADC output driver

supplies to avoid modulating the clock signal with digital noise.

If the clock is generated from another type of source (by gating,

dividing, or other methods), retime it using the original clock at

the last step. See the AN-501 Application Note and the AN-756

Application Note for more in-depth information about jitter

performance as it relates to ADCs.

Figure 58 shows the estimated SNR of the AD6679 across input

frequency for different clock induced jitter values. Estimate the

SNR by using the following equation:























 −











 −

10log

(dBFS)

JITTER

ADC

SNR

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