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AD6679 Datasheet(PDF) 11 Page - Analog Devices |
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AD6679 Datasheet(HTML) 11 Page - Analog Devices |
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11 / 81 page  Data Sheet AD6679 Rev. B | Page 11 of 81 CLK+ DCO± (DATA CLOCK OUTPUT) 0° PHASE ADJUST DCO± (DATA CLOCK OUTPUT) 180° PHASE ADJUST SYNC+ APERTURE DELAY N N + x N + 33 N + 34 N + 35 D13± D0± CONVERTER 0 SAMPLE [N] VIN±x OVR OVR OVR OVR OVR OVR OVR OVR D13 D13 D13 D13 D13 D13 D13 D0 D0 D0 D0 D0 D0 D0 CLK– SYNC– OVR+ (OVERRANGE/STATUS BIT) OVR– tCLK tCH tDCO tPD tSKEWF tSKEWR CONVERTER 1 SAMPLE [N] CONVERTER 0 SAMPLE [N + 1] CONVERTER 1 SAMPLE [N + 1] CONVERTER 0 SAMPLE [N + 2] SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET STATUS BIT SELECTED BY OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0] IN THE REGISTER MAP D13 D0 Figure 5. Parallel Interleaved Mode—Two Virtual Converters (Decimate by 1) |
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