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AD6679

Data Sheet

Rev. B | Page 22 of 81

Pin No.

Mnemonic

Type

Description

CMOS Outputs

J14, J1

FD_A, FD_B

Output

Fast Detect Outputs for Channel A and Channel B.

Digital Inputs

C7, C8

SYNC+,

SYNC−

Input

Active High LVDS Sync Input—True/Complement.

Data Outputs

N9, P9

A D0/D1−,

A D0/D1+

Output

LVDS Channel A Data 0/Data 1 Output Data—

Complement/True.

N10, P10

A D2/D3−,

A D2/D3+

Output

LVDS Channel A Data 2/Data 3 Output Data—

Complement/True.

N11, P11

A D4/D5−,

A D4/D5+

Output

LVDS Channel A Data 4/Data 5 Output Data—

Complement/True.

N12, P12

A D6/D7−,

A D6/D7+

Output

LVDS Channel A Data 6/Data 7 Output Data—

Complement/True.

N13, P13

A D8/D9−,

A D8/D9+

Output

LVDS Channel A Data 8/Data 9 Output Data—

Complement/True.

N14, P14

A D10/D11−,

A D10/D11+

Output

LVDS Channel A Data 10/Data 11 Output Data—

Complement/True.

M13, M14

A D12/D13−,

A D12/D13+

Output

LVDS Channel A Data 12/Data 13 Output Data—

Complement/True.

N6, P6

B D0/D1−,

B D0/D1+

Output

LVDS Channel B Data 0/Data 1 Output Data—

Complement/True.

M2, M1

B D2/D3−,

B D2/D3+

Output

LVDS Channel B Data 2/Data 3 Output Data—

Complement/True.

N1, P1

B D4/D5−,

B D4/D5+

Output

LVDS Channel B Data 4/Data 5 Output Data—

Complement/True.

N2, P2

B D6/D7−,

B D6/D7+

Output

LVDS Channel B Data 6/Data 7 Output Data—

Complement/True.

N3, P3

B D8/D9−,

B D8/D9+

Output

LVDS Channel B Data 8/Data 9 Output Data—

Complement/True.

N4, P4

B D10/D11−,

B D10/D11+

Output

LVDS Channel B Data 10/Data 11 Output Data—

Complement/True.

N5, P5

B D12/D13−,

B D12/D13+

Output

LVDS Channel B Data 12/Data 13 Output Data—

Complement/True.

L13, L14

OVR−, OVR+

Output

LVDS Overrange Output Data—Complement/True.

K13, K14

DCO−, DCO+

Output

LVDS Digital Clock Output Data—Complement/True.

DUT Controls

SDIO

Input/output

SPI Serial Data Input/Output.

SCLK

Input

SPI Serial Clock.

CSB

Input

SPI Chip Select (Active Low).

J13

PDWN/STBY

Input

Power-Down Input (Active High). The operation of this

pin depends on the SPI mode and can be configured in

power-down or standby mode.

When using channel multiplexed (even/odd) LVDS mode for one converter, the Channel B outputs are disabled and can be left unconnected.

AD6679 Datasheet(PDF) 22 Page - Analog Devices

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