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Z80 Datasheet(PDF) 104 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 104 Page - Zilog, Inc. |
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104 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access Interrupt On Ready Normally, when the DMA has been enabled by the CPU to request the bus while the I/O device’s Ready line is inactive, the Ready line’s transition to the active state causes the BUSREQ line to go Low (Figure 65). It does so within two clock cycles if the setup time to the rising edge of CLK is met. This does not take place, however, when the Interrupt on Ready option (also called the Interrupt Before Requesting Bus option) is selected. When this option is used, the DMA interrupts the CPU when the Ready line comes active. The CPU’s interrupt service routine now writes control bytes to the DMA, which enable the DMA to request the bus after the service routine finishes. As noted earlier, the CPU cannot respond to an interrupt when the DMA is bus master. Thus, when enabled in Continuous mode, the DMA inter- rupts the CPU when the Ready line first becomes active, but not on succeeding transitions. The Interrupt on Ready option is typically used to put new starting addresses into the DMA, so that transfers go to a part of memory that is dynamically determined. Interrupt Service Routines In addition to the DMA’s extensive programmability for mode-setting (usually done at power-up initialization), numerous commands (control bytes) are designed for use in various interrupt service routines. The next chapter on “Programming,” fully explains the commands, but a quick overview follows. Some typical functions for which control bytes are available for use in interrupt service routines include: • Reset the DMA – Enable the DMA for bus requesting – Disable the DMA for bus requesting |
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