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Z80 Datasheet(PDF) 108 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 108 Page - Zilog, Inc. |
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108 / 330 page ![]() <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access Figure 38. Polling for a Service Request Bit PROGRAMMING Overview The DMA must be programmed before use. Its control registers have no useful default values at power-up. In addition, commands are frequently written to the DMA after the initial power-up programming sets basic DMA operating modes; this is most commonly done within service routines for purposes such as reading status, changing starting addresses, and reenabling both interrupt and bus-request logic after a block transfer or search. The DMA has two primary states that can be set: (1) an enabled state, in which the DMA gains control of the system buses and directs data transfers between ports or data searching from a single port; and (2) a disabled state, in which the DMA initiates neither bus requests nor data transfers. Table 13 describes these states and their substates in detail. When the DMA is powered-up or reset by any means, it is automatically placed into the disabled state. Program commands can be written to it by the CPU in the enable/inactive state, but this automatically puts the DMA into the disabled state, which is maintained until an ENABLE DMA command is written by the CPU to the DMA’s Write Register 6 (WR6). In the Z80 Family, the DMA normally exists as a peripheral device in system I/O space. Its Chip Enable (CE) signal is decoded from the lower byte of the address bus for this purpose and all control bytes and status bytes are written to and read from the same I/O port address, using an output instruction such as OTIR (in the Z80 CPU). It is possible to use the DMA in memory mapped I/O structures, but this involves some external logic, which is explained in the “Applications” |
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