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Z80 Datasheet(PDF) 110 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 110 Page - Zilog, Inc. |
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110 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access Write Registers Control bytes must be written to all relevant registers in the DMA at power- up initialization. This section describes and illustrates each of the write registers, WR0 through WR6, to which control bytes can be written. The convention of calling the control bytes written to WR6 “commands” is often used, because they are commonly used within CPU interrupt service routines and at other times during system operation in addition to their use at power-up initialization of the DMA. “Internal Structure” on page 71 gives an organizational overview of the write registers (Figure 30) and describes the access method. Control bytes are written to one or more of the write register groups (WR6-WR0) by first writing a byte to the “base register” in that group. All groups have base registers and most groups have additional associated registers. The asso- ciated registers in a group are sequentially accessed by first writing a byte to the base register. The base register byte contains both control bits for DMA function control, and pointer bits (1s) to one or more of the asso- ciated registers in the base register’s group. Figure 39 for WR0 illustrates this. In this figure, the sequence in which associated registers within a group can be written to is shown by the vertical position of the associated registers. For example, if a byte written to the DMA contains the bits that identify WR0 (bits D0, D1, and D7), and also contains 1s in the bit positions that point to associated registers 2 and 4, then the next two bytes written to the DMA after the base register byte is stored in these two associated registers, in that order. Figure 40 through Figure 46 illustrate and describe each of seven base registers and their associated registers. These figures, unlike Figure 30, do not include the 16-bit counters associated with the starting-address and block-length registers. |
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